Design for an IO block array in a tile-based FPGA
文献类型：期刊论文
| 作者 | Ding Guangxin ; Chen Lingdou ; Liu Zhongli |
| 刊名 | 半导体学报
 |
| 出版日期 | 2009 |
| 卷号 | 30期号:8页码:141-146 |
| 中文摘要 | a design for an io block array in a tile-based fpga is presented.corresponding with the characteristics of the fpga, each io cell is composed of a signal path, local routing pool and configurable input/output buffers.shared programmable registers in the signal path can be configured for the function of jtag, without specific boundary scan registers/latches, saving layout area.the local routing pool increases the flexibility of routing and the routability of the whole fpga.an auxiliary power supply is adopted to increase the performance of the io buffers at different configured io standards.the organization of the io block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.this design strategy facilitates the design of fpgas with different capacities or architectures in an fpga family series.the bond-out schemes of the same fpga chip in different packages are also considered.the layout is based on smic 0.13μm logic 1p8m salicide 1.2/2.5 v cmos technology.our performance is comparable with commercial sram-based fpgas which use a similar process. |
| 英文摘要 | a design for an io block array in a tile-based fpga is presented.corresponding with the characteristics of the fpga, each io cell is composed of a signal path, local routing pool and configurable input/output buffers.shared programmable registers in the signal path can be configured for the function of jtag, without specific boundary scan registers/latches, saving layout area.the local routing pool increases the flexibility of routing and the routability of the whole fpga.an auxiliary power supply is adopted to increase the performance of the io buffers at different configured io standards.the organization of the io block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.this design strategy facilitates the design of fpgas with different capacities or architectures in an fpga family series.the bond-out schemes of the same fpga chip in different packages are also considered.the layout is based on smic 0.13μm logic 1p8m salicide 1.2/2.5 v cmos technology.our performance is comparable with commercial sram-based fpgas which use a similar process.; 于2010-11-23批量导入; zhangdi于2010-11-23 12:59:55导入数据到semi-ir的ir; made available in dspace on 2010-11-23t04:59:55z (gmt). no. of bitstreams: 1 3669.pdf: 588546 bytes, checksum: 248474b14a2740e699775ecdaf02c656 (md5) previous issue date: 2009; institute of semiconductors,chinese academy of sciences |
| 学科主题 | 微电子学 |
| 收录类别 | CSCD |
| 语种 | 英语 |
| 公开日期 | 2010-11-23 ; 2011-04-28 |
| 源URL | [http://ir.semi.ac.cn/handle/172111/15721]  |
| 专题 | 半导体研究所_中国科学院半导体研究所（2009年前） |
| 推荐引用方式 GB/T 7714 | Ding Guangxin,Chen Lingdou,Liu Zhongli. Design for an IO block array in a tile-based FPGA[J]. 半导体学报,2009,30(8):141-146. |
| APA | Ding Guangxin,Chen Lingdou,&Liu Zhongli.(2009).Design for an IO block array in a tile-based FPGA.半导体学报,30(8),141-146. |
| MLA | Ding Guangxin,et al."Design for an IO block array in a tile-based FPGA".半导体学报 30.8(2009):141-146. |
入库方式： OAI收割
来源：半导体研究所
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