A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction
文献类型：期刊论文
| 作者 | Yan Xiaozhou ; Kuang Xiaofei ; Wu Nanjian |
| 刊名 | 半导体学报
 |
| 出版日期 | 2009 |
| 卷号 | 30期号:4页码:99-103 |
| 中文摘要 | this paper proposes a fast-settling frequency-presetting pll frequency synthesizer. a mixed-signal vco and a digital processor are developed to accurately preset the frequency of vco and greatly reduce the settling time. an auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. the digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. a 1.2 ghz integer-n synthesizer with 1 mhz reference input was implemented in a 0.18μm process. the measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dbc/hz@1mhz.the reference spur is -52 dbc. |
| 英文摘要 | this paper proposes a fast-settling frequency-presetting pll frequency synthesizer. a mixed-signal vco and a digital processor are developed to accurately preset the frequency of vco and greatly reduce the settling time. an auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. the digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. a 1.2 ghz integer-n synthesizer with 1 mhz reference input was implemented in a 0.18μm process. the measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is -108 dbc/hz@1mhz.the reference spur is -52 dbc.; 于2010-11-23批量导入; zhangdi于2010-11-23 13:00:09导入数据到semi-ir的ir; made available in dspace on 2010-11-23t05:00:09z (gmt). no. of bitstreams: 1 3727.pdf: 200530 bytes, checksum: ff0e5609943b132492e55e6c6f0df904 (md5) previous issue date: 2009; the special funds for state key development for basic research of china,国家自然科学基金; institute of semiconductors, chinese academy of sciences |
| 学科主题 | 微电子学 |
| 收录类别 | CSCD |
| 资助信息 | the special funds for state key development for basic research of china,国家自然科学基金 |
| 语种 | 英语 |
| 公开日期 | 2010-11-23 ; 2011-04-28 |
| 源URL | [http://ir.semi.ac.cn/handle/172111/15805]  |
| 专题 | 半导体研究所_中国科学院半导体研究所（2009年前） |
| 推荐引用方式 GB/T 7714 | Yan Xiaozhou,Kuang Xiaofei,Wu Nanjian. A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction[J]. 半导体学报,2009,30(4):99-103. |
| APA | Yan Xiaozhou,Kuang Xiaofei,&Wu Nanjian.(2009).A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction.半导体学报,30(4),99-103. |
| MLA | Yan Xiaozhou,et al."A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction".半导体学报 30.4(2009):99-103. |
入库方式： OAI收割
来源：半导体研究所
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