Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device
文献类型：期刊论文
| 作者 | Li GQ ; Qian F ; Ruan H ; Liu LR(刘立人) |
| 刊名 | appl. optics
 |
| 出版日期 | 1999 |
| 卷号 | 38期号:23页码:5039 |
| 关键词 | CONTENT-ADDRESSABLE-MEMORY SYMBOLIC SUBSTITUTION NEGABINARY REPRESENTATION IMPLEMENTATION MULTIPLICATION SUBTRACTION OPERATIONS ALGORITHM ADDER |
| ISSN号 | 0003-6935 |
| 中文摘要 | a compact two-step modified-signed-digit arithmetic-logic array processor is proposed. when the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. the optical implementation and experimental demonstration with an electron-trapping device are shown. each digit is encoded by a single pixel, and no polarization is included. any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. the system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (c) 1999 optical society of america. |
| 语种 | 英语 |
| WOS记录号 | WOS:000081922400011 |
| 公开日期 | 2009-09-18 |
| 源URL | [http://ir.siom.ac.cn/handle/181231/1574]  |
| 专题 | 上海光学精密机械研究所_信息光学开放实验室 |
| 推荐引用方式 GB/T 7714 | Li GQ,Qian F,Ruan H,et al. Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device[J]. appl. optics,1999,38(23):5039, 5045. |
| APA | Li GQ,Qian F,Ruan H,&刘立人.(1999).Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device.appl. optics,38(23),5039. |
| MLA | Li GQ,et al."Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device".appl. optics 38.23(1999):5039. |
入库方式： OAI收割
来源：上海光学精密机械研究所
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