X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing
文献类型：期刊论文
| 作者 | Jia Li; Qiang Xu; Yu Hu; Xiaowei Li |
| 刊名 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
 |
| 出版日期 | 2010 |
| 卷号 | 18期号:7页码:1081-1092 |
| 英文摘要 | Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capturephases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely "iFill", to address the above issue, by analyzing the impact of X-bits on switching activities of the circuit nodes in the two different phases. In addition, different from prior X-filling methods for shift-power reduction that can only reduce shift-in power, our method is able to cut down power consumptions in both shift-in and shift-out processes. Experimental results on benchmark circuits show that the proposed technique can guarantee the power safety in both shiftand capture phases during at-speed scan-based testing. |
| 收录类别 | SCI |
| 原文出处 | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5200343 |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/2752]  |
| 专题 | 深圳先进技术研究院_集成所 |
| 作者单位 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
| 推荐引用方式 GB/T 7714 | Jia Li,Qiang Xu,Yu Hu,et al. X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2010,18(7):1081-1092. |
| APA | Jia Li,Qiang Xu,Yu Hu,&Xiaowei Li.(2010).X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,18(7),1081-1092. |
| MLA | Jia Li,et al."X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.7(2010):1081-1092. |
入库方式： OAI收割
来源：深圳先进技术研究院
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