Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint
文献类型：期刊论文
| 作者 | Li Jiang; Qiang Xu; Krishnendu Chakrabarty; T. M. Mak |
| 刊名 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
 |
| 出版日期 | 2012 |
| 英文摘要 | We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated with three-dimensional (3-D) integration technology. In contrast to prior work, we consider the pre-bond testpin- count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for test-access mechanisms. In addition, a thermalaware test scheduling algorithm is proposed to eliminate hot spots during manufacturing test. Experimental results for the ITC’02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution. |
| 收录类别 | SCI |
| 原文出处 | http://www.cs.sjtu.edu.cn/~jiangli/paper/jiang-tvlsi.pdf |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/3770]  |
| 专题 | 深圳先进技术研究院_集成所 |
| 作者单位 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
| 推荐引用方式 GB/T 7714 | Li Jiang,Qiang Xu,Krishnendu Chakrabarty,et al. Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2012. |
| APA | Li Jiang,Qiang Xu,Krishnendu Chakrabarty,&T. M. Mak.(2012).Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. |
| MLA | Li Jiang,et al."Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2012). |
入库方式： OAI收割
来源：深圳先进技术研究院
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