Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
文献类型：会议论文
| 作者 | Li Jiang; Qiang Xu; Krishnendu Chakrabarty; T. M. Mak |
| 出版日期 | 2009 |
| 会议名称 | 2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009 |
| 英文摘要 | We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for a test-access mechanism in 3D technology. Experimental results for the ITC'02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution. |
| 收录类别 | EI |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/2504]  |
| 专题 | 深圳先进技术研究院_集成所 |
| 作者单位 | 2009 |
| 推荐引用方式 GB/T 7714 | Li Jiang,Qiang Xu,Krishnendu Chakrabarty,et al. Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint[C]. 见:2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009. |
入库方式： OAI收割
来源：深圳先进技术研究院
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