Stochastic Wire-Length Model with TSV Placement on Periphery Area
文献类型：会议论文
| 作者 | Ling, Jianhui; Li, Huiyun; Xu, Guoqing; Xiong, Liying |
| 出版日期 | 2014 |
| 会议名称 | Proceedings of the 16th Electronics Packaging Technology Conference, EPTC 2014 |
| 会议地点 | 新加坡 |
| 英文摘要 | Despite of numerous advantages of three dimensional integrated circuits (3D-ICs), their commercial success remains limited. The reason lies, in part, on the lack of physical design tools about Through-Silicon-Vias (TSVs) and 3D die stacking. In this paper, we propose a novel TSV placement method on the periphery of the dies. Based on this method, we derive a novel mathematical model to estimate 3D-IC wire-length and area with TSVs before floor-planning. We analyze the impact of TSVs on silicon area and wire-length. A case study with ISCAS benchmark circuits demonstrates that the proposed TSV placement method reduces the chip area and alleviates the reliability issues. |
| 收录类别 | EI |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/5561]  |
| 专题 | 深圳先进技术研究院_集成所 |
| 作者单位 | 2014 |
| 推荐引用方式 GB/T 7714 | Ling, Jianhui,Li, Huiyun,Xu, Guoqing,et al. Stochastic Wire-Length Model with TSV Placement on Periphery Area[C]. 见:Proceedings of the 16th Electronics Packaging Technology Conference, EPTC 2014. 新加坡. |
入库方式： OAI收割
来源：深圳先进技术研究院
浏览0
下载0
收藏0
其他版本
除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。