High-Throughput Cost-Effective and Low-Power AES Chip Design
文献类型：会议论文
| 作者 | Yunping Liang; Ye Li; Chengmin Zhang |
| 出版日期 | 2010 |
| 会议名称 | 3rd International Conference on BioMedical Engineering and Informatics, BMEI 2010 |
| 会议地点 | Yantai, China |
| 英文摘要 | This paper proposes a high-throughput cost-effective and low-power implementation of AES (Advanced Encryption Standard) supporting encryption and decryption with 128-bit cipher key. Considering the cost-effective and low-power, resource-sharing scheme is employed to reduce the hardware complexity of the cipher and decipher. In addition, we adopt composite field arithmetic solution to implement SubByte/InvSubByte and byte-level structure to implement MixColumns/InvMixColumns transformation. Considering the high-throughput, we present a mixed pipelining architecture with both inner-round and outer-round pipelining for 10 iteration rounds of operation. The performance is evaluated on SMIC 0.18um CMOS technology and the throughput achieves at 8Gbps with the cost of only 17519 equivalent NAND2 gates, and the power consumption is only 9.7mw. |
| 收录类别 | EI |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/3040]  |
| 专题 | 深圳先进技术研究院_医工所 |
| 作者单位 | 2010 |
| 推荐引用方式 GB/T 7714 | Yunping Liang,Ye Li,Chengmin Zhang. High-Throughput Cost-Effective and Low-Power AES Chip Design[C]. 见:3rd International Conference on BioMedical Engineering and Informatics, BMEI 2010. Yantai, China. |
入库方式： OAI收割
来源：深圳先进技术研究院
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