Resistance and Inductance Calculations of the Tapered Through Silicon Vias
文献类型：会议论文
| 作者 | Yuanjun Liang; Ye Li |
| 出版日期 | 2010 |
| 会议名称 | 12th Electronics Packaging Technology Conference |
| 会议地点 | Singapore |
| 英文摘要 | Abstract In this paper, formulas are proposed to calculate the parasitic resistance and inductance of the tapered Through Silicon Vias (TSVs). The expressions are developed as the functions of the via height, radius, and the distance between vias and the slope angle of the via walls. The comparison between the formula calculation and numerical electromagnetic simulation results shows that the maximum error is less than 3%, revealing the formulas have high accurate. These formulas provide an efficient way to optimize the impedance of the signal and power paths when using tapered TSVs in Three-Dimensional Integrated Circuits (3DICs) |
| 收录类别 | EI |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/3042]  |
| 专题 | 深圳先进技术研究院_医工所 |
| 作者单位 | 2010 |
| 推荐引用方式 GB/T 7714 | Yuanjun Liang,Ye Li. Resistance and Inductance Calculations of the Tapered Through Silicon Vias[C]. 见:12th Electronics Packaging Technology Conference. Singapore. |
入库方式： OAI收割
来源：深圳先进技术研究院
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