A 12-bit 1.74-mW 20-MS/s DAC with Resisitor-string and Current- Steering Hybrid Architecture
文献类型：会议论文
| 作者 | Bill Ma; Qinjin Huang; Fengqi Yu |
| 出版日期 | 2015 |
| 会议名称 | IEEE SOCC2015 |
| 会议地点 | Beijing |
| 英文摘要 | This paper presents a novel segmented hybrid digital-to-analog converter (DAC). It uses a resistor-string as the LSB part for low-power consumption, and uses a current- steering array as the MSB part for high-speed and small size. The LSB and MSB parts are combined by a slew-rate-enhanced class AB output amplifier for high speed. Compared to resistor string DACs, current steering DACs, or resistor-capacitor hybrid DACs, the proposed DAC shows a better tradeoff between power and speed at low power application demanding a sampling clock between 1 MHz and 100 MHz. The prototype is a 12-bit DAC implemented in 0.18-μm CMOS technology with the worst measured DNL/INL of 6.38 LSB / 7.55 LSB. The analogue part power consumption is 1.24 mW and the digital part 0.5mW at 1.35-V power supply at 20-MS/s sampling rate. Its output is single-end buffered voltage with a range of 500 mV. The core area is 0.16 mm 2 . |
| 收录类别 | EI |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/7277]  |
| 专题 | 深圳先进技术研究院_医工所 |
| 作者单位 | 2015 |
| 推荐引用方式 GB/T 7714 | Bill Ma,Qinjin Huang,Fengqi Yu. A 12-bit 1.74-mW 20-MS/s DAC with Resisitor-string and Current- Steering Hybrid Architecture[C]. 见:IEEE SOCC2015. Beijing. |
入库方式： OAI收割
来源：深圳先进技术研究院
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