A novel high-speed divide-by-3/4 prescaler
文献类型：会议论文
| 作者 | Wenjian Jiang; Fengqi Yu |
| 出版日期 | 2016 |
| 会议名称 | IMCEC2016 |
| 会议地点 | Xian |
| 英文摘要 | A novel extended true single-phase clock-based (ETSPC) divide-by-3/4 prescaler is presented. Instead of using the conventional topologies (e.g. transmission gates, logic gates), the pass transistor logic circuit is applied. Thus only two transistors are needed to implement the mode selection control. The operation speed is improved by reducing of the critical path delay between the ETSCP flip-flops. Since the number of additional transistors compared with divide-by-4 prescaler, only two transistors are added. Therefore low power consumption can be achieved. Simulation results in a standard 180nm CMOS process show that the operation speed of the proposed divide-by-3/4 prescaler is 15.9%~103% faster than the conventional divide-by-3/4 prescaler |
| 收录类别 | EI |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/10601]  |
| 专题 | 深圳先进技术研究院_医工所 |
| 作者单位 | 2016 |
| 推荐引用方式 GB/T 7714 | Wenjian Jiang,Fengqi Yu. A novel high-speed divide-by-3/4 prescaler[C]. 见:IMCEC2016. Xian. |
入库方式： OAI收割
来源：深圳先进技术研究院
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