4.2 GHz 0.81 mW triple-modulus prescaler based on true single-phase clock
文献类型：期刊论文
| 作者 | Jiang, Wenjian; Yu, Fengqi |
| 刊名 | ELECTRONICS LETTERS
 |
| 出版日期 | 2016 |
| 英文摘要 | A dual-modulus prescaler based on true single-phase clock D flip-flop is presented. Instead of using the conventional digital logic circuit, the pass transistor logic circuit is applied to reduce the number of the transistors and the power of the divider. By adding only two additional transistors, a dual-modulus operation is achieved. Implemented in a standard 180 nm CMOS process, the proposed divide-by 6/7/8 prescaler based on the proposed dual-modulus one achieves an operating frequency of 4.2 GHz with a measured power consumption of 0.81 mW for a 1.2 V supply. |
| 收录类别 | SCI |
| 原文出处 | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7481037&tag=1 |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/10439]  |
| 专题 | 深圳先进技术研究院_医工所 |
| 作者单位 | ELECTRONICS LETTERS |
| 推荐引用方式 GB/T 7714 | Jiang, Wenjian,Yu, Fengqi. 4.2 GHz 0.81 mW triple-modulus prescaler based on true single-phase clock[J]. ELECTRONICS LETTERS,2016. |
| APA | Jiang, Wenjian,&Yu, Fengqi.(2016).4.2 GHz 0.81 mW triple-modulus prescaler based on true single-phase clock.ELECTRONICS LETTERS. |
| MLA | Jiang, Wenjian,et al."4.2 GHz 0.81 mW triple-modulus prescaler based on true single-phase clock".ELECTRONICS LETTERS (2016). |
入库方式： OAI收割
来源：深圳先进技术研究院
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