基于CPCI Express的网络型并行处理机研制
文献类型：学位论文
| 作者 | 张骋 |
| 学位类别 | 博士 |
| 答辩日期 | 2008-05-30 |
| 授予单位 | 中国科学院声学研究所 |
| 授予地点 | 声学研究所 |
| 关键词 | 并行处理 FPGA协处理 PCIe交换网络 千兆以太网 SOPC |
| 其他题名 | A Network Type of Parallel Signal Processing System Based on CPCI Express |
| 学位专业 | 信号与信息处理 |
| 中文摘要 | 一个国家工业控制的发展，雷达声纳装备的研制，必须要有自己的信号处理机作支持。随着科学技术的发展，大规模并行处理机已经成为当前信号处理的首要解决方案。并行处理机的性能与三点紧密相关：处理单元、互连结构和并行任务分配方法。第三点与软件开发系统相关，比如虚拟单处理器技术能够大大简化并行系统的开发工作。本文主要着重讨论处理单元和互连结构两大关键因素。 本文阐述了基于CPCI Express标准架构网络型并行处理机的设计，它是在海军第一代水声装备标准信号处理机基础上发展而来的。在第一阶段，我们继承第一代处理机结构，采用性能强大的处理芯片，实现了基本型处理机。该处理机已经研制成功，并且已应用于多个雷达声纳装备中。与同类型国外产品相比性能基本持平，此外还实现了某些特有功能模块。基于Cache结构的PCI管理总线结构，使得主机能够快速访问处理板上资源。基于PCI总线的支撑软件系统，更是大大降低了算法开发的难度，成为基本型处理机的一大优势。 在前期技术经验的积累下，结合FPGA的最新技术和第三代互连总线的发展，我们提出了利用FPGA强大的协处理能力，以及PCI Express交换网络灵活互连结构的网络型处理机。FPGA内在微结构的高度并行性在处理并行算法时非常有效，可重构性能够灵活地适应算法。本文以FPGA-FFT处理机为例，阐述了其设计结构以及与DSP处理器的性能比较；讲述了协处理原型开发，并结合DSP操作系统软件和FPGA协处理硬件，设计了一种DSP与FPGA协同处理模型。 互连结构关系到处理机中各单元的通信效率，直接影响并行系统加速比。我们从低到高分三个层次阐述了互连设计。首先是处理单元内部的LINK口互连；其次是处理单元间的PCIe交换网络；最后是处理机与其他系统间通信的千兆以太网接入。我们在FPGA中分别实现了这三个层次互连协议，本文阐述了它们的设计结构，测试了通信效率，并对性能改进做了基本分析。 并行处理机的设计是一个复杂过程，涉及技术覆盖了当今计算机发展的诸多领域，受限篇幅不能一一详尽描述。希望本文的研究成果能够为中国并行处理机的发展做出自己的一点点贡献。 |
| 英文摘要 | The development of industry control, radar and sonar equipments for one country, must be supported by his own signal processing system. With the advance of science and technology, large-scale parallel system became the primary solution. The performance of system is associated with three points: processing units, interconnect fabric and distribution of parallel tasks. The third is related with development software, for example, the technology of virtual single processor can simplify it greatly. This paper focused on two key points: processing units and interconnect fabric. The network type of parallel signal processing system based on CPCI Express devveloped from Navy's first generation of underwater acoustic equipment standard system. At first stage, we inherited the structure of first generation, applied more powerful processing chip to implement the basic type system. It has been used in several radar or sonar equipments. Compared to the similar foreign system, it has almost the same performance, plus some unique functions. The PCI management structure based on cache, make host access processing board very efficient. The supporting software reduce the difficulty of the algorithm development greatly, became a huge advantage of basic type system. Under the accumulation of early technical experience, combined the latest FPGA technology with third-generation interconnect bus development, we raised a new network type of parallel signal processing system, which makes use of powerful FPGA co-processing capacity and PCI Express flexible switch network interconnection structure. FPGA internal micro-structure of high degree parallelism, make it very effective in parallel processing algorithms, its reconfiguration brings the flexibility to adapt to various algorithm. In this paper, FPGA-FFT processor for example, described the design structure as well as its performance comparison with DSP processors. It also introduced the co-processing prototype development. As software and hardware co-processing combined DSP operating system with FPGA, we designed a DSP and FPGA synergistic processing model. Interconnect fabric between the processors related to the communication efficiency of structure elements, direct impact on the parallel system’s speedup performance. From low to high, we describe three levels of interconnection. The first is LINK in the processing units; followed by the PCIe switch network between processing units; and the final is Gigabit Ethernet access forming communication between processing system and others. We implemented these three levels of interconnection protocol in FPGA. This paper describes the structure of their design, testing the efficiency of communication and makes a basic analysis about performance improvement. Parallel processing system design is a complex process, involving various areas of current computer technology development. And limited to paper space, we can not make a detailed description for every respect. Hope that this research can contribute to the development of Chinese parallel processing system a little. |
| 语种 | 中文 |
| 公开日期 | 2011-05-07 |
| 页码 | 134 |
| 源URL | [http://159.226.59.140/handle/311008/344]  |
| 专题 | 声学研究所_声学所博硕士学位论文_1981-2009博硕士学位论文 |
| 推荐引用方式 GB/T 7714 | 张骋. 基于CPCI Express的网络型并行处理机研制[D]. 声学研究所. 中国科学院声学研究所. 2008. |
入库方式： OAI收割
来源：声学研究所
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