基于DRAM的存储系统性能研究与优化
文献类型：学位论文
| 作者 | 逄珺 |
| 学位类别 | 博士 |
| 答辩日期 | 2008-05-30 |
| 授予单位 | 中国科学院声学研究所 |
| 授予地点 | 声学研究所 |
| 关键词 | 存储系统 性能 突发调度 公平性 多核 |
| 其他题名 | Performance Analysis and Improvement of DRAM Based Memory System |
| 学位专业 | 信号与信息处理 |
| 中文摘要 | 现代计算机系统的性能越来越受到存储系统性能的限制。当处理器的性能以每年60%的速度增长时，存储芯片的带宽的增长率只有10%左右，使得存储带宽很难满足处理器性能的要求。本文的中心思想就是如何从硬件角度优化存储系统的设计以及性能。 针对现代存储器DRAM的特点，本文给出了一种通用的SDRAM控制器的硬件设计方案。该SDRAM控制器可与多种不同时间参数、地址范围、突发长度等的SDRAM协同工作。大大减少存储系统设计中的重复工作。 存储系统性能的主要衡量标准是带宽和延时。本文提出了一种基于优先级表达式的突发调度算法(PEB_Burst)。该调度算法创造性的将三个重要的bank内部仲裁因素突发等待时间、突发长度、读写突发的优先级综合考虑建立了一个优先级表达式，根据该表达式进行bank内部仲裁。为了使表达式适用于读写访存，该算法为每个bank内部写访存也建立了一个突发队列。通过M5模拟器运行SPEC CPU2000和STREAM得到的数据表明PEB_Burst算法在数据总线利用率方面比FR-FCFS调度、突发调度以及顺序访存分别高出6%、9%和74%。在执行时间方面，比FR-FCFS调度、突发调度以及顺序执行分别减少10%、5%和41%。PEB_Burst调度算法在改善存储系统性能方面具有很好的优越性。 当处理器发展到多核的阶段，各个核共享存储的结构使得处理器访存出现许多新特点。本文分析了PEB_Burst算法在多核系统中的性能特点。通过在M5模拟器中的仿真得出结论，在多核系统中，当访存量变大时，PEB_Burst调度算法的优势更加明显。同时，我们研究了PEB_Burst算法的公平性问题，分析了原因，并实现了考虑公平性的调度策略。实验结果证明，带有公平性的PEB_Burst调度算法明显改善了其在多核系统中的访存不公平问题，不公平性系数下降了56.64％。 |
| 英文摘要 | The performance of modern computer system is greatly limited by the bandwidth of DRAM-based memory. This thesis tries to optimize the performance of memory system and solves the bottleneck of bandwidth. A configurable SDRAM controller is designed to reduce the duplicate work of memory system design. The controller can work with SDRAM of different data width, address arrange, time parameters and burst length. It is verified with different kinds of MICRON SDRAM models and works well. Altering the sequence of main memory accesses can reduce observed access latency, therefore improve data bus utilization. While previous reordering mechanisms consider factors related to memory access separately, this thesis proposes a priority-expression based burst scheduling(PEB_Burst). It groups several factors together to build a priority expression for bank arbitration based on burst scheduling. To make the expression suitable for both read and write accesses, write queue in a bank is designed to buffer bursts. Experiment results from a modified M5 simulator running selected SPEC CPU2000 and STREAM benchmarks show that the PEB_Burst scheduling improves the bus utilization about 10%, 5% and 74% and reduces the execution time 10%, 5% and 41% over the FR-FCFS， burst scheduling and conventional in-order memory scheduling. The PEB_Burst scheduling is proved to be feasible. When we enter the multicore era in computer science, the share-memory system shows some new characteristics. The performance of PEB_Burst in multicore system is also evaluated and analyzed. Experiments results from M5 simulator present that PEB_Burst scheduling has much more advantages with more memory accesses in multicore system. The fairness problem of PEB_Burst scheduling is also described and analyzed. A fair PEB_Burst scheduling is implemented. Simulation results from M5 simulator show that the fairness value of PEB_Burst is reduced by 56.64％, which is a greatly improvement. |
| 语种 | 中文 |
| 公开日期 | 2011-05-07 |
| 页码 | 79 |
| 源URL | [http://159.226.59.140/handle/311008/394]  |
| 专题 | 声学研究所_声学所博硕士学位论文_1981-2009博硕士学位论文 |
| 推荐引用方式 GB/T 7714 | 逄珺. 基于DRAM的存储系统性能研究与优化[D]. 声学研究所. 中国科学院声学研究所. 2008. |
入库方式： OAI收割
来源：声学研究所
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