A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis
文献类型：期刊论文
| 作者 | Liu, Meng ; Zhang, Zhiwei; Sun, Wenqin; Wang, Donglin
|
| 刊名 | IEICE ELECTRONICS EXPRESS
 |
| 出版日期 | 2017-10-25 |
| 卷号 | 14期号:20 |
| 关键词 | Symmetrical Clock Tree Multiple Fan-out Matching Algorithm Buffer Insertion Obstacle-aware Placement And Routing |
| DOI | 10.1587/elex.14.20170935 |
| 文献子类 | Article |
| 英文摘要 | Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design. |
| WOS研究方向 | Engineering |
| 语种 | 英语 |
| WOS记录号 | WOS:000418382100012 |
| 资助机构 | Chinese Academy of Sciences(XDA-06010402) |
| 源URL | [http://ir.ia.ac.cn/handle/173211/21929]  |
| 专题 | 自动化研究所_国家专用集成电路设计工程技术研究中心 |
| 作者单位 | Univ Chinese Acad Sci, Chinese Acad Sci, Inst Automat, Beijing 100190, Peoples R China |
| 推荐引用方式 GB/T 7714 | Liu, Meng,Zhang, Zhiwei,Sun, Wenqin,et al. A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis[J]. IEICE ELECTRONICS EXPRESS,2017,14(20). |
| APA | Liu, Meng,Zhang, Zhiwei,Sun, Wenqin,&Wang, Donglin.(2017).A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis.IEICE ELECTRONICS EXPRESS,14(20). |
| MLA | Liu, Meng,et al."A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis".IEICE ELECTRONICS EXPRESS 14.20(2017). |
入库方式： OAI收割
来源：自动化研究所
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