Fault Injection Method and Voter Design for Dual Modual Redundancy FPGA Hardening
文献类型：会议论文
| 作者 | Zheng, Meisong ; Wang, Zilong; Li, Lijian
|
| 出版日期 | 2016-06 |
| 会议日期 | 2016-6-17 |
| 会议地点 | Beijing |
| 关键词 | Fpga Fault Tolerance Fault Injection Redundancy |
| 英文摘要 | Hardware overhead and system reliability has always been in a dilemma in the world of FPGA designing. This paper provides a hardware overhead free dual modular redundancy (DMR) voter scheme using the abundant and unused carry chains in Xilinx FPGAs. And the experimental evaluation on MCNC benchmarks are carried on real FPGA and logic-simulation based fault injection method, respectively. Experimental results under the two methods are identical; hence validates the effectiveness of logic-simulation method and the DMR hardening scheme we have designed. |
| 会议录 | IEEE International Conference on Election Information and Emergency Communication
 |
| 源URL | [http://ir.ia.ac.cn/handle/173211/11749]  |
| 专题 | 自动化研究所_空天信息研究中心 |
| 通讯作者 | Li, Lijian |
| 作者单位 | 中国科学院自动化研究所 |
| 推荐引用方式 GB/T 7714 | Zheng, Meisong,Wang, Zilong,Li, Lijian. Fault Injection Method and Voter Design for Dual Modual Redundancy FPGA Hardening[C]. 见:. Beijing. 2016-6-17. |
入库方式： OAI收割
来源：自动化研究所
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