low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan
文献类型：期刊论文
| 作者 | Zhang Zhen-Dong ; Wu Bin ; Zhou Yu-Mei ; Zhang Xin |
| 刊名 | VLSI Design
 |
| 出版日期 | 2012 |
| 卷号 | 2012页码:- |
| ISSN号 | 1065-514X |
| 关键词 | CMOS integrated circuits Harmonic analysis Standards |
| 中文摘要 | A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm2, and the synthesized maximal working frequency is 400MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility. Copyright © 2012 Zhen-dong Zhang et al. |
| 英文摘要 | A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm2, and the synthesized maximal working frequency is 400MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility. Copyright © 2012 Zhen-dong Zhang et al. |
| 收录类别 | EI |
| 语种 | 英语 |
| 公开日期 | 2013-09-17 |
| 源URL | [http://ir.iscas.ac.cn/handle/311060/15413]  |
| 专题 | 软件研究所_软件所图书馆_期刊论文 |
| 推荐引用方式 GB/T 7714 | Zhang Zhen-Dong,Wu Bin,Zhou Yu-Mei,et al. low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan[J]. VLSI Design,2012,2012:-. |
| APA | Zhang Zhen-Dong,Wu Bin,Zhou Yu-Mei,&Zhang Xin.(2012).low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan.VLSI Design,2012,-. |
| MLA | Zhang Zhen-Dong,et al."low-complexity hardware interleaver/deinterleaver for ieee 802.11a/g/n wlan".VLSI Design 2012(2012):-. |
入库方式： OAI收割
来源：软件研究所
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