A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler.
文献类型：期刊论文
| 作者 | Jiang, Wenjian; Yu, Fengqi; Huang, Qinjin |
| 刊名 | IEICE ELECTRONICS EXPRESS
 |
| 出版日期 | 2017 |
| 文献子类 | 期刊论文 |
| 英文摘要 | A novel low-power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. Compared with the conventional topologies, one of the precharge stages in the TSPC flip-flops is eliminated, and the number of switching stages is reduced to 5. The prescaler is implemented in a standard 0.18-mu m CMOS process. It achieves the maximum operating frequency of 5.7 GHz with a measured power consumption of 0.95 mW and 0.98 mW in divide-by-3 mode and divide-by-2 mode, respectively, when operated at 1.5-V power supply. Keywords: dual-modulus prescaler, TSPC, high-speed, low-power |
| URL标识 | 查看原文 |
| 语种 | 英语 |
| 源URL | [http://ir.siat.ac.cn:8080/handle/172644/12013]  |
| 专题 | 深圳先进技术研究院_医工所 |
| 作者单位 | IEICE ELECTRONICS EXPRESS |
| 推荐引用方式 GB/T 7714 | Jiang, Wenjian,Yu, Fengqi,Huang, Qinjin. A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler.[J]. IEICE ELECTRONICS EXPRESS,2017. |
| APA | Jiang, Wenjian,Yu, Fengqi,&Huang, Qinjin.(2017).A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler..IEICE ELECTRONICS EXPRESS. |
| MLA | Jiang, Wenjian,et al."A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler.".IEICE ELECTRONICS EXPRESS (2017). |
入库方式： OAI收割
来源：深圳先进技术研究院
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