An avs hdtv video decoder architecture employing efficient hw/sw partitioning
文献类型：期刊论文
| 作者 | Jia, Huizhu; Zhang, Peng; Xie, Don; Gao, Wen |
| 刊名 | Ieee transactions on consumer electronics
 |
| 出版日期 | 2006-11-01 |
| 卷号 | 52期号:4页码:1447-1453 |
| ISSN号 | 0098-3063 |
| 关键词 | Avs Hw/sw partition Video decoder Hdtv |
| 通讯作者 | Jia, huizhu(hzjia@jdl.ac.cn) |
| 英文摘要 | In this paper, we propose an optimized realtime a vs (a chinese next-generation audio/video coding standard) hdtv video decoder. the decoder has been implemented in a single soc with hw/sw partitioning. avs algorithms and complexity are first analyzed. based on the analysis, a hardware implementation of the mb level 7-stage pipeline is selected. the software tasks are realized with a 32-bit risc processor. we further propose the optimization of interface and risc processor based on the proposed architecture. the avs decoder (risc processor and hardware accelerators) is described in high-level verilog/vhdl hardware description language and implemented in a single-chip a vs hdtv real-time decoder. at 148.5mhz working frequency, the decoder chip can support real-time decoding of ntsc, pal or hdtv (720p@60 frames/s or 1080i@60 fields/s) bit-streams. finally, the decoder has been fully tested on a prototyping board.(1) |
| WOS研究方向 | Engineering ; Telecommunications |
| WOS类目 | Engineering, Electrical & Electronic ; Telecommunications |
| 语种 | 英语 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| WOS记录号 | WOS:000243211000045 |
| URI标识 | http://www.irgrid.ac.cn/handle/1471x/2378545 |
| 专题 | 中国科学院大学 |
| 通讯作者 | Jia, Huizhu |
| 作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, Beijing, Peoples R China 2.Chinese Acad Sci, Grad Sch, Beijing, Peoples R China |
| 推荐引用方式 GB/T 7714 | Jia, Huizhu,Zhang, Peng,Xie, Don,et al. An avs hdtv video decoder architecture employing efficient hw/sw partitioning[J]. Ieee transactions on consumer electronics,2006,52(4):1447-1453. |
| APA | Jia, Huizhu,Zhang, Peng,Xie, Don,&Gao, Wen.(2006).An avs hdtv video decoder architecture employing efficient hw/sw partitioning.Ieee transactions on consumer electronics,52(4),1447-1453. |
| MLA | Jia, Huizhu,et al."An avs hdtv video decoder architecture employing efficient hw/sw partitioning".Ieee transactions on consumer electronics 52.4(2006):1447-1453. |
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来源：中国科学院大学
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