A hardware-efficient multi-resolution block matching algorithm and its vlsi architecture for high definition mpeg-like video encoders
文献类型：期刊论文
| 作者 | Yin, Haibing1,2; Jia, Huizhu2; Qi, Honggang3; Ji, Xianghu2; Xie, Xiaodong2; Gao, Wen2 |
| 刊名 | Ieee transactions on circuits and systems for video technology
 |
| 出版日期 | 2010-09-01 |
| 卷号 | 20期号:9页码:1242-1254 |
| 关键词 | Architecture Audio video coding standard (avs) H.264 Multi-resolution motion estimation Very large scale integration (vlsi) Video coding |
| ISSN号 | 1051-8215 |
| DOI | 10.1109/tcsvt.2010.2058476 |
| 通讯作者 | Yin, haibing(yinhb@cjlu.edu.cn) |
| 英文摘要 | High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. this paper proposes an efficient very large scale integration architecture for integer multi-resolution motion estimation based on optimized algorithm. there are three major contributions in this paper. first, this paper proposes a hardware friendly multi-resolution motion estimation algorithm well-suited for high definition video encoder. second, parallel processing element (pe) array structure is proposed to implement three-level hierarchical motion estimation, only 256 pes are enough for one reference frame real-time high definition motion estimation by efficient pe reuse. third, efficient on-chip reference pixel buffer sharing mechanism between integer and fractional motion estimation is proposed with almost 50% sram saving and memory bandwidth reduction. the proposed multi-resolution motion estimation algorithm reached a good balance between complexity and performance with rate distortion optimized variable block size motion estimation support. also, we have achieved moderate logic circuit and on-chip sram consumption. the proposed architecture is well-suited for all mpeg-like video coding standards such as h. 264, audio video coding standard, and vc-1. |
| WOS关键词 | MOTION ESTIMATION ALGORITHM ; DATA-REUSE ; H.264/AVC ENCODER ; DESIGN ; IMPLEMENTATION ; CMOS |
| WOS研究方向 | Engineering |
| WOS类目 | Engineering, Electrical & Electronic |
| 语种 | 英语 |
| WOS记录号 | WOS:000283591000008 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| URI标识 | http://www.irgrid.ac.cn/handle/1471x/2407795 |
| 专题 | 中国科学院大学 |
| 通讯作者 | Yin, Haibing |
| 作者单位 | 1.China Jiliang Univ, Sch Elect Engn, Hangzhou, Zhejiang, Peoples R China 2.Peking Univ, Natl Engn Lab Video Technol, Beijing 100871, Peoples R China 3.Chinese Acad Sci, Grad Univ, Beijing 100049, Peoples R China |
| 推荐引用方式 GB/T 7714 | Yin, Haibing,Jia, Huizhu,Qi, Honggang,et al. A hardware-efficient multi-resolution block matching algorithm and its vlsi architecture for high definition mpeg-like video encoders[J]. Ieee transactions on circuits and systems for video technology,2010,20(9):1242-1254. |
| APA | Yin, Haibing,Jia, Huizhu,Qi, Honggang,Ji, Xianghu,Xie, Xiaodong,&Gao, Wen.(2010).A hardware-efficient multi-resolution block matching algorithm and its vlsi architecture for high definition mpeg-like video encoders.Ieee transactions on circuits and systems for video technology,20(9),1242-1254. |
| MLA | Yin, Haibing,et al."A hardware-efficient multi-resolution block matching algorithm and its vlsi architecture for high definition mpeg-like video encoders".Ieee transactions on circuits and systems for video technology 20.9(2010):1242-1254. |
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来源：中国科学院大学
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