Performance-asymmetry-aware scheduling for chip multiprocessors with static core coupling
文献类型：期刊论文
| 作者 | Dong, Jianbo1,2; Zhang, Lei1; Han, Yinhe1,2; Yan, Guihai1,2; Li, Xiaowei1,2 |
| 刊名 | Journal of systems architecture
 |
| 出版日期 | 2010-10-01 |
| 卷号 | 56期号:10页码:534-542 |
| 关键词 | Process variation Thread-level redundancy Chip multiprocessor Scheduling |
| ISSN号 | 1383-7621 |
| DOI | 10.1016/j.sysarc.2010.09.003 |
| 通讯作者 | Han, yinhe(yinhes@gmail.com) |
| 英文摘要 | Thread-level redundancy is an efficient approach for transient fault detection and recovery in chip multiprocessors (cmps), in which two adjacent cores are statically coupled to form a functional dual modular redundancy (dmr). manufacturing process variations cause core-to-core (c2c) performance asymmetry across the chip, which can be further divided into the asymmetry among core-pairs and the asymmetry within a core-pair. we call them inter- and intra-pair asymmetries, respectively, both of which should be taken into considerations in application scheduling for cmps with static core coupling. in this paper, we first formulate the above scheduling problem as a 0-1 programming problem to maximize the system weighted throughput. an efficient ivf&appsen algorithm is then proposed, which we prove to be optimal when the number of applications equals to that of core-pairs. we also adapt the simulated annealing technique to tackle this problem when applications are less than core-pairs on chip. simulations on a 64-core cmp shows that the proposed algorithms achieve 2.5-9.3% improvement in weighted throughput when compared to prior varf&appipc algorithm. (c) 2010 elsevier b.v. all rights reserved. |
| WOS研究方向 | Computer Science |
| WOS类目 | Computer Science, Hardware & Architecture ; Computer Science, Software Engineering |
| 语种 | 英语 |
| WOS记录号 | WOS:000284570600005 |
| 出版者 | ELSEVIER SCIENCE BV |
| URI标识 | http://www.irgrid.ac.cn/handle/1471x/2411690 |
| 专题 | 中国科学院大学 |
| 通讯作者 | Han, Yinhe |
| 作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing, Peoples R China 2.Chinese Acad Sci, Grad Univ, Beijing, Peoples R China |
| 推荐引用方式 GB/T 7714 | Dong, Jianbo,Zhang, Lei,Han, Yinhe,et al. Performance-asymmetry-aware scheduling for chip multiprocessors with static core coupling[J]. Journal of systems architecture,2010,56(10):534-542. |
| APA | Dong, Jianbo,Zhang, Lei,Han, Yinhe,Yan, Guihai,&Li, Xiaowei.(2010).Performance-asymmetry-aware scheduling for chip multiprocessors with static core coupling.Journal of systems architecture,56(10),534-542. |
| MLA | Dong, Jianbo,et al."Performance-asymmetry-aware scheduling for chip multiprocessors with static core coupling".Journal of systems architecture 56.10(2010):534-542. |
入库方式： iSwitch采集
来源：中国科学院大学
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