A programmable vision chip based on multiple levels of parallel processors
文献类型：期刊论文
| 作者 | Zhang, Wancheng; Fu, Qiuyu; Wu, Nan-Jian |
| 刊名 | Ieee journal of solid-state circuits
 |
| 出版日期 | 2011-09-01 |
| 卷号 | 46期号:9页码:2132-2147 |
| 关键词 | Cmos sensor Image recognition Massive parallel Simd Vision chip |
| ISSN号 | 0018-9200 |
| DOI | 10.1109/jssc.2011.2158024 |
| 通讯作者 | Zhang, wancheng() |
| 英文摘要 | This paper proposes a novel programmable vision chip based on multiple levels of parallel processors. the chip integrates cmos image sensor, multiple-levels of simd parallel processors and an embedded microprocessor unit (mpu). the multiple-levels of simd parallel processors consist of an array processor of simd processing elements (pes) and a column of simd row processors (rps). the pe array and rps have an o(n x n) parallelism and an o(n) parallelism, respectively. the pe array and rps can be reconfigured to handle algorithms with different complexities and processing speeds. the pe array, rps and mpu can execute low-, mid- and high-level image processing algorithms, respectively, which efficiently increases the performance of the vision chip. the vision chip can satisfy flexibly the needs of different vision applications such as image pre-processing, complicated feature extraction and over 1000 fps high-speed image capture. a prototype chip with 128 x 28 image sensor, 128 a/d converters, 32 8-bit rps and 32 x 128 pes is fabricated using the 0.18 mu m cmos process. applications including target tracking, pattern extraction and image recognition are demonstrated. |
| WOS关键词 | RECOGNITION SYSTEMS ; FEATURE-EXTRACTION ; IMAGE ; SENSOR ; ARCHITECTURE ; DESIGN ; ARRAY ; VLSI |
| WOS研究方向 | Engineering |
| WOS类目 | Engineering, Electrical & Electronic |
| 语种 | 英语 |
| WOS记录号 | WOS:000294169700016 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| URI标识 | http://www.irgrid.ac.cn/handle/1471x/2428406 |
| 专题 | 半导体研究所 |
| 通讯作者 | Zhang, Wancheng |
| 作者单位 | Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China |
| 推荐引用方式 GB/T 7714 | Zhang, Wancheng,Fu, Qiuyu,Wu, Nan-Jian. A programmable vision chip based on multiple levels of parallel processors[J]. Ieee journal of solid-state circuits,2011,46(9):2132-2147. |
| APA | Zhang, Wancheng,Fu, Qiuyu,&Wu, Nan-Jian.(2011).A programmable vision chip based on multiple levels of parallel processors.Ieee journal of solid-state circuits,46(9),2132-2147. |
| MLA | Zhang, Wancheng,et al."A programmable vision chip based on multiple levels of parallel processors".Ieee journal of solid-state circuits 46.9(2011):2132-2147. |
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来源：半导体研究所
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