A Digital Regulator for FPGA Implementation
文献类型：会议论文
| 作者 | Qian, Xiang-ping2; Qiao, Wei-ming1; Zhou, Zhong-zu1 ; Chen, Xi-meng2; Jing, Lan1; Zhang, CS
|
| 出版日期 | 2012 |
| 关键词 | digital regulator carry look-ahead adder booth algorithm Wallace tree |
| 卷号 | 433-440 |
| DOI | 10.4028/www.scientific.net/AMR.433-440.4547 |
| 页码 | 4547-+ |
| 英文摘要 | A digital regulator architecture implemented in FPGA is described which is used in the accelerator power supply. To save the delay time, the device is based on combinational circuit and special data format. The multiplier uses the partial products generated by modified Booth algorithm, Carry look-ahead adder and Wallace tree. The regulator is written in Verilog, and is synthesized into FPGA. The synthesis results shows that the proposed regulator can run 200MHZ clock rate in FPGA EP3C25F256 and the whole feedback time is as short as 3 clock periods. |
| 会议录 | MATERIALS SCIENCE AND INFORMATION TECHNOLOGY, PTS 1-8
 |
| 会议录出版者 | TRANS TECH PUBLICATIONS LTD |
| 会议录出版地 | KREUZSTRASSE 10, 8635 DURNTEN-ZURICH, SWITZERLAND |
| 语种 | 英语 |
| WOS研究方向 | Computer Science ; Engineering ; Materials Science |
| WOS记录号 | WOS:000302092001285 |
| 源URL | [http://119.78.100.186/handle/113462/58569]  |
| 专题 | 中国科学院近代物理研究所 |
| 通讯作者 | Qiao, Wei-ming |
| 作者单位 | 1.Chinese Acad Sci, Inst Modern Phys, Lanzhou, Gansu, Peoples R China 2.Lanzhou Univ, Sch Nucl Sci & Technol, Lanzhou, Gansu, Peoples R China |
| 推荐引用方式 GB/T 7714 | Qian, Xiang-ping,Qiao, Wei-ming,Zhou, Zhong-zu,et al. A Digital Regulator for FPGA Implementation[C]. 见:. |
入库方式： OAI收割
来源：近代物理研究所
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