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A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

文献类型：期刊论文

作者Wei, Xing2,3,5; Yu, Le4; Yin, Tao3,5; Huang, Zhihong3,5; Li, Wei1,3; Yang, Haigang3,5
刊名INTEGRATION-THE VLSI JOURNAL
出版日期2019-05-01
卷号66页码:164-172
关键词Floating-point Fast fourier transform (FFT) Mixed-radix Multi-path delay feedback (MDF) Binary-tree decomposition Twiddle factor Fused FP arithmetic unit
ISSN号0167-9260
DOI10.1016/j.vlsi.2019.02.008
英文摘要This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2(k)-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm(2). The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.
资助项目National Natural Science Foundation of China[61876172] ; National Natural Science Foundation of China[61704173] ; Major Program of Beijing Science and Technology[Z171100000117019] ; Beijing Key Laboratory of Big Data Technology for Food Safety, Beijing Technology and Business University[BKBD-2017KF05]
WOS研究方向Computer Science ; Engineering
语种英语
WOS记录号WOS:000469905300017
出版者ELSEVIER SCIENCE BV
源URL[http://119.78.100.204/handle/2XEOYT63/4215]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Yu, Le; Yang, Haigang
作者单位1.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China
2.China Acad Elect & Informat Technol, Beijing 100041, Peoples R China
3.Univ Chinese Acad Sci, Beijing 100049, Peoples R China
4.Beijing Technol & Business Univ, Beijing Key Lab Big Data Technol Food Safety, Beijing 100048, Peoples R China
5.Chinese Acad Sci, Inst Elect, Beijing 100190, Peoples R China
推荐引用方式
GB/T 7714		 Wei, Xing,Yu, Le,Yin, Tao,et al. A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition[J]. INTEGRATION-THE VLSI JOURNAL,2019,66:164-172.
APA Wei, Xing,Yu, Le,Yin, Tao,Huang, Zhihong,Li, Wei,&Yang, Haigang.(2019).A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition.INTEGRATION-THE VLSI JOURNAL,66,164-172.
MLA Wei, Xing,et al."A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition".INTEGRATION-THE VLSI JOURNAL 66(2019):164-172.

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来源：计算技术研究所

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