Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
文献类型：期刊论文
| 作者 | Elio Guidetti; Wei-Wu Hu(胡伟武); Ji-Ye Zhao(赵继业); Shi-Qiang Zhong(钟石强); Xu Yang(杨旭); Chris Wu(吴永强) |
| 刊名 | Journal of Computer Science and Technology
 |
| 出版日期 | 2007 |
| 卷号 | 22期号:1页码:1 |
| 关键词 | General-purpose Processor Superscalar Pipeline Out-of-order Execution Non-blocking Cache Physical Design Synthesis Flow Bit-sliced Placement |
| 英文摘要 | This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bit-sliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500. |
| 语种 | 英语 |
| 公开日期 | 2010-11-02 |
| 源URL | [http://ictir.ict.ac.cn/handle/311040/821]  |
| 专题 | 中国科学院计算技术研究所期刊论文_2007年英文 |
| 推荐引用方式 GB/T 7714 | Elio Guidetti,Wei-Wu Hu,Ji-Ye Zhao,et al. Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology[J]. Journal of Computer Science and Technology,2007,22(1):1. |
| APA | Elio Guidetti,Wei-Wu Hu,Ji-Ye Zhao,Shi-Qiang Zhong,Xu Yang,&Chris Wu.(2007).Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.Journal of Computer Science and Technology,22(1),1. |
| MLA | Elio Guidetti,et al."Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology".Journal of Computer Science and Technology 22.1(2007):1. |
入库方式： OAI收割
来源：计算技术研究所
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