In this study, a hetero-tunneling gFET with an ultra-shallow pocket junction has been developed, as shown in Fig.1. The gFET was fabricated in a 8inch (100) silicon (Si) substrate, as shown in Fig.2. After LOCOS formation, silicon-germanium (Si1-xGex) and Si cap layer were grown on Si substrate using selective epitaxy. After source implantation, an ultra-shallower pocket is formed by using of the Ge preamorphization implantation (PAI), ultra low energy implantation and spike annealing.