Provided are a CMOS device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the CMOS semiconductor device includes an n-type device and a p-type device. The n-type device and the p-type device each may include: a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the n-type device or the p-type device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. For the n-type device, the PTS layer has net negative charges, and for the p-type device, the PTS layer has net positive charges.