Sigma Delta A/D转换器和锁相环的设计
文献类型：学位论文
| 作者 | 李罗生 |
| 学位类别 | 博士 |
| 答辩日期 | 2005 |
| 授予单位 | 中国科学院声学研究所 |
| 授予地点 | 中国科学院声学研究所 |
| 关键词 | 调制器 过采样 锁相环 时钟抖动 |
| 其他题名 | Design of Sigma Delta A/D Converter and PLL |
| 中文摘要 | 本论文主要内容包括SigmaDelta结构A／D转换器的设计实现和锁相环的设计实现两部分。按结构划分，A／D转换器的种类很多，其中最近十多年来发展起来的sigmaDelta结构，相对于其它结构类型，更容易实现高分辨率。目前14bit以上有效分辨率的A／D转换器大部分采用这种结构。论文采用0.18μm的CMOS混合信号工艺设计了一种2-1-1（一个两阶和两个一阶）级联四阶一位量化结构的SigmaDeltaA／D转换器，其电路主要由sigmaDelta调制器、抽样滤波器和外部接口电路三部分组成。调制器是模拟电路，它具有对量化噪声的整形作用，把信号带宽内的低频量化噪声搬移到高频段，抽样滤波器则为数字电路，它以一定的速率抽取调制器的输出信号，并且滤除高频噪声。外部接口电路包括并行接口和SPI串行接口两种方式。该A／D转换器完成了实验性流片，芯片采用小尺寸TQFP封装，测试结果表明，在64MHz采样时钟，32倍过采样的条件下，能达到ZMS／s的转换率、86dB动态范围、80dB的信噪比（SNR）和79dB的信噪失真比（SNDR）。该SigmaDeltaA／D转换器中，调制器面积为1.7平方毫米，数字部分面积为3平方毫米左右，总功耗为Z10mw，其中模拟部分功耗为110mW。锁相环在现代的电子电路系统中应用非常广泛，是高速处理器（包括CPU或DSP）中不可缺少的一部分，能起时钟倍频作用。论文用0.18μm的CMOS逻辑工艺完成了锁相环的设计。锁相环（PLL）完成实验流片，测试结果表明，锁相环压控振荡器VCO输出范围是loMHz-600MHz，在该输出范围内RMSjitter小于15ps，peak-peakjitter小于80ps（输出15oMHz左右时钟时，RMSjitter为7ps，peak-peakjitter为50ps）。锁相环的版图大小为560μm*400μm，功耗为6mW左右。 |
| 英文摘要 | This paper mainly includes two parts, implementation of Sigma Delta A/D converter and implementation of a PLL. A/D converter has various types of architecture. Sigma Delta appears in the recent ten years. Compared to other types of architecture, it can more easily achieve high resolution. In the present, most A/D converter products of more than 14bit resolution are implemented with sigma delta architecture. This paper presents the design of a fourth order sigma delta A/D converter with the topology of 2-1-1 cascaded single bit quantization, with 0.18/im CMOS mixed signal process. The circuits include three parts, the sigma delta modulator, the decimation filter and the external interface circuits. The modulator is mainly made of analog circuits and its noise shaping effect can move the quantization noise in signal bandwidth of low frequency to band of high frequency. The circuits of decimation filter is digital, it samples the signal from the modulator and rejects the noise of high frequency. The interface circuits include the parallel mode and serial SPI mode. The A/D converter has successfully been taped out and packaged as TQFP. The test result showed that it can achieve converter rate of 2MS/s, DR of 86dB, SNR of 80dB and SNDR of 79dB, when the sampling clock is 64MHz and oversampling rate is 32. The area of the analog sigma delta modulator and digital decimation filter are about 1.7 mm2 and 3mm2 respectively. The total power dissipation is about 210mW and the analog part is 110mW. PLLs are widely used in modern electronic circuits and systems. It can multiply the frequency of clocks and is an indispensable internal block of microprocessor, includes CPU and DSP. PLL presented by this paper is implemented with 0.18μm CMOS process. The test result of the PLL chip showed that the output range of the VCO is 10MHz-.600MHz. The RMS jitter is less than 15ps and peak-peak jitter is less than 80ps in the output range. The RMS jitter of the PLL is 7ps and peak-peak jitter is less than 50ps, when output 150MHz clock. The area of the active layout of the PLL is 560μm*400μm, power consumption is about 6mW. |
| 语种 | 中文 |
| 公开日期 | 2011-05-07 |
| 页码 | 104 |
| 源URL | [http://159.226.59.140/handle/311008/910]  |
| 专题 | 声学研究所_声学所博硕士学位论文_1981-2009博硕士学位论文 |
| 推荐引用方式 GB/T 7714 | 李罗生. Sigma Delta A/D转换器和锁相环的设计[D]. 中国科学院声学研究所. 中国科学院声学研究所. 2005. |
入库方式： OAI收割
来源：声学研究所
浏览0
下载0
收藏0
其他版本
除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。