A Programmable Vision Chip Based on Multiple Levels of Parallel Processors
文献类型：期刊论文
| ; | |
| 作者 | Zhang WC; Fu QY; Wu NJ; Zhang, WC (reprint author), Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China, nanjian@red.semi.ac.cn |
| 刊名 | ieee journal of solid-state circuits
 ; IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
| 出版日期 | 2011 ; 2011 |
| 卷号 | 46期号:9页码:2132-2147 |
| 关键词 | RECOGNITION SYSTEMS FEATURE-EXTRACTION IMAGE SENSOR ARCHITECTURE DESIGN ARRAY VLSI Recognition Systems Feature-extraction Image Sensor Architecture Design Array Vlsi |
| ISSN号 | 0018-9200 ; 0018-9200 |
| 通讯作者 | zhang, wc (reprint author), chinese acad sci, inst semicond, state key lab superlattices & microstruct, beijing 100083, peoples r china, nanjian@red.semi.ac.cn |
| 英文摘要 | This paper proposes a novel programmable vision chip based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit (MPU). The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N x N) parallelism and an O(N) parallelism, respectively. The PE array and RPs can be reconfigured to handle algorithms with different complexities and processing speeds. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively, which efficiently increases the performance of the vision chip. The vision chip can satisfy flexibly the needs of different vision applications such as image pre-processing, complicated feature extraction and over 1000 fps high-speed image capture. A prototype chip with 128 x 28 image sensor, 128 A/D converters, 32 8-bit RPs and 32 x 128 PEs is fabricated using the 0.18 mu m CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated. |
| 学科主题 | 半导体物理 ; 半导体物理 |
| 收录类别 | SCI |
| 资助信息 | national natural science foundation of china[60976023]; chinese national high-tech researching and development projection[2008aa010703]; special funds for major state basic research project of china[2011cb932902] |
| 语种 | 英语 ; 英语 |
| 资助机构 | National Natural Science Foundation of China[60976023]; Chinese National High-Tech Researching and Development Projection[2008AA010703]; special funds for Major State Basic Research Project of China[2011CB932902] |
| 公开日期 | 2012-01-06 ; 2012-01-06 |
| 源URL | [http://ir.semi.ac.cn/handle/172111/22665]  |
| 专题 | 半导体研究所_半导体超晶格国家重点实验室 |
| 通讯作者 | Zhang, WC (reprint author), Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China, nanjian@red.semi.ac.cn |
| 推荐引用方式 GB/T 7714 | Zhang WC,Fu QY,Wu NJ,et al. A Programmable Vision Chip Based on Multiple Levels of Parallel Processors, A Programmable Vision Chip Based on Multiple Levels of Parallel Processors[J]. ieee journal of solid-state circuits, IEEE JOURNAL OF SOLID-STATE CIRCUITS,2011, 2011,46, 46(9):2132-2147, 2132-2147. |
| APA | Zhang WC,Fu QY,Wu NJ,&Zhang, WC .(2011).A Programmable Vision Chip Based on Multiple Levels of Parallel Processors.ieee journal of solid-state circuits,46(9),2132-2147. |
| MLA | Zhang WC,et al."A Programmable Vision Chip Based on Multiple Levels of Parallel Processors".ieee journal of solid-state circuits 46.9(2011):2132-2147. |
入库方式： OAI收割
来源：半导体研究所
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