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A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators

文献类型：期刊论文

作者Wang, Ying; Li, Huawei; Li, Xiaowei
刊名IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
出版日期2018-10-01
卷号37期号:10页码:1971-1984
关键词Convolutional neural network (CNN) deep learning low power memory subsystem
ISSN号0278-0070
DOI10.1109/TCAD.2017.2778060
英文摘要The rapid development of machine learning is enabling a plenty of novel applications, such as image and speech recognition for embedded and mobile devices. However, state-of-the-art deep learning models like convolutional neural networks (CNNs) are demanding so much on-chip storage and compute resources that they cannot be smoothly handled by low-power mobile or embedded systems. In order to fit large CNN models into mobile or more cutting-edge devices for IoT or cyberphysics applications, we proposed an efficient on-chip memory architecture for CNN inference acceleration, and showed its application to in-house single-instruction multiple-data structure machine learning processor. The redesigned on-chip memory subsystem, Memsqueezer, includes an active weight buffer and data buffer set that embraces specialized compression methods to reduce the footprint of CNN parameters (weights) and activation data, respectively. Memsqueezer buffer can compress the data and weight set according to the dataflow in computation, and it also includes a built-in redundancy detection mechanism that actively scans through the working-set of CNNs to boost their inference performance by eliminating the computation redundancy in CNN models. In our experiments, it is shown that the CNN processors with Memsqueezer buffers achieve more than 2x performance improvement and reduces 85% energy consumption on average over the conventional buffer design with the same area budget.
资助项目National Natural Science Foundation of China[61432017] ; National Natural Science Foundation of China[61504153] ; National Natural Science Foundation of China[61532017] ; National Natural Science Foundation of China[61402146] ; National Natural Science Foundation of China[61521092] ; National Key Research and Development Program of China[2016YFF0203500]
WOS研究方向Computer Science ; Engineering
语种英语
WOS记录号WOS:000445264200005
出版者IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
源URL[http://119.78.100.204/handle/2XEOYT63/4916]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Li, Huawei; Li, Xiaowei
作者单位Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
推荐引用方式
GB/T 7714		 Wang, Ying,Li, Huawei,Li, Xiaowei. A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2018,37(10):1971-1984.
APA Wang, Ying,Li, Huawei,&Li, Xiaowei.(2018).A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,37(10),1971-1984.
MLA Wang, Ying,et al."A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 37.10(2018):1971-1984.

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来源：计算技术研究所

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