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A Non-Stop Double Buffering Mechanism for Dataflow Architecture

文献类型：期刊论文

作者Tan, Xu2,3; Shen, Xiao-Wei2,3; Ye, Xiao-Chun2,4; Wang, Da2; Fan, Dong-Rui2,3; Zhang, Lunkai1; Li, Wen-Ming2; Zhang, Zhi-Min2; Tang, Zhi-Min2
刊名JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
出版日期2018
卷号33期号:1页码:145-157
ISSN号1000-9000
关键词non-stop double buffering dataflow architecture high-performance computing
DOI10.1007/s11390-017-1747-6
英文摘要Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataflow architecture achieves a 16.2% average efficiency improvement over that without the optimization.
资助项目National Key Research and Development Program of China[2016YFB0200501] ; National Natural Science Foundation of China[61332009] ; National Natural Science Foundation of China[61521092] ; Open Project Program of State Key Laboratory of Mathematical Engineering and Advanced Computing[2016A04] ; Beijing Municipal Science and Technology Commission[Z15010101009]
WOS研究方向Computer Science
语种英语
出版者SCIENCE PRESS
WOS记录号WOS:000423587100009
源URL[http://119.78.100.204/handle/2XEOYT63/6188]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Fan, Dong-Rui
作者单位1.Univ Chicago, Dept Comp Sci, Chicago, IL 60637 USA
2.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
3.Univ Chinese Acad Sci, Sch Comp & Control Engn, Beijing 100049, Peoples R China
4.State Key Lab Math Engn & Adv Comp, Wuxi 214125, Peoples R China
推荐引用方式
GB/T 7714		 Tan, Xu,Shen, Xiao-Wei,Ye, Xiao-Chun,et al. A Non-Stop Double Buffering Mechanism for Dataflow Architecture[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2018,33(1):145-157.
APA Tan, Xu.,Shen, Xiao-Wei.,Ye, Xiao-Chun.,Wang, Da.,Fan, Dong-Rui.,...&Tang, Zhi-Min.(2018).A Non-Stop Double Buffering Mechanism for Dataflow Architecture.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,33(1),145-157.
MLA Tan, Xu,et al."A Non-Stop Double Buffering Mechanism for Dataflow Architecture".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 33.1(2018):145-157.

入库方式： OAI收割

来源：计算技术研究所

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