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LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

文献类型：期刊论文

作者Hu, Yu1,2; Ye, Jing2; Shi, Zhiping1,3; Li, Xiaowei2
刊名IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
出版日期2017-02-01
卷号E100D期号:2页码:323-331
关键词process variation timing variation sample path selection least square
ISSN号1745-1361
DOI10.1587/transinf.2016EDP7184
英文摘要Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.
资助项目National Natural Science Foundation of China (NSFC)[61532017] ; National Natural Science Foundation of China (NSFC)[61376043] ; National Natural Science Foundation of China (NSFC)[61274030]
WOS研究方向Computer Science
语种英语
WOS记录号WOS:000399370700009
出版者IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
源URL[http://119.78.100.204/handle/2XEOYT63/7285]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Shi, Zhiping
作者单位1.Capital Normal Univ, Beijing Adv Innovat Ctr Imaging Technol, Beijing 100048, Peoples R China
2.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
3.Capital Normal Univ, Coll Informat Engn, Beijing 100048, Peoples R China
推荐引用方式
GB/T 7714		 Hu, Yu,Ye, Jing,Shi, Zhiping,et al. LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,2017,E100D(2):323-331.
APA Hu, Yu,Ye, Jing,Shi, Zhiping,&Li, Xiaowei.(2017).LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization.IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,E100D(2),323-331.
MLA Hu, Yu,et al."LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization".IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E100D.2(2017):323-331.

入库方式： OAI收割

来源：计算技术研究所

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