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A New Binary-Halved Clustering Method and ERT Processor for ASSR System

文献类型：期刊论文

作者Chou, Chih-Hung1; Kuan, Ta-Wen1; Barma, Shovan1; Chen, Bo-Wei1; Ji, Wen2; Peng, Chih-Hsiang1; Wang, Jhing-Fa1
刊名IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
出版日期2016-05-01
卷号24期号:5页码:1871-1884
关键词Automatic speech-speaker recognition (ASSR) binary-halved clustering (BHC) configurable processing element (CPE) extraction recognition and training (ERT) multichannel router (MCR) multifeedback shift register (MFSR)
ISSN号1063-8210
DOI10.1109/TVLSI.2015.2479259
英文摘要This paper presents an automatic speech-speaker recognition (ASSR) system implemented in a chip which includes a built-in extraction, recognition, and training (ERT) core. For VLSI design (here, ASSR system), the hardware cost and time complexity are always the important issues which are improved in this proposed design in two levels: 1) algorithmic and 2) architecture. At the algorithm level, a newly binary-halved clustering (BHC) is proposed to achieve low time complexity and low memory requirement. In addition, at the architecture level, a new ERT core is proposed and implemented based on data dependence and reuse mechanism to reduce the time and hardware cost as well. Finally, the chip implementation is synthesized, placed, and routed using TSMC 90-nm technology library. To verify the performance of the proposed BHC method, a case study is performed based on nine speakers. Moreover, the validation of the ASSR system is examined in two parts: 1) speech recognition and 2) speaker recognition. The results show that the proposed system can achieve 93.38% and 87.56% of recognition rates during speech and speaker recognition, respectively. Furthermore, the proposed ASSR chip includes 396k gate counts, and consumes power in 8.74 mW. Such results demonstrate that the performance of the proposed ASSR system is superior to the conventional systems.
WOS研究方向Computer Science ; Engineering
语种英语
WOS记录号WOS:000375278300022
出版者IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
源URL[http://119.78.100.204/handle/2XEOYT63/8521]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Chou, Chih-Hung; Kuan, Ta-Wen; Barma, Shovan; Chen, Bo-Wei; Ji, Wen; Peng, Chih-Hsiang; Wang, Jhing-Fa
作者单位1.Natl Cheng Kung Univ, Dept Elect Engn, 1 Univ Rd, Tainan 70101, Taiwan
2.Chinese Acad Sci, Inst Comp Technol, Beijing 100864, Peoples R China
推荐引用方式
GB/T 7714		 Chou, Chih-Hung,Kuan, Ta-Wen,Barma, Shovan,et al. A New Binary-Halved Clustering Method and ERT Processor for ASSR System[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2016,24(5):1871-1884.
APA Chou, Chih-Hung.,Kuan, Ta-Wen.,Barma, Shovan.,Chen, Bo-Wei.,Ji, Wen.,...&Wang, Jhing-Fa.(2016).A New Binary-Halved Clustering Method and ERT Processor for ASSR System.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,24(5),1871-1884.
MLA Chou, Chih-Hung,et al."A New Binary-Halved Clustering Method and ERT Processor for ASSR System".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24.5(2016):1871-1884.

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来源：计算技术研究所

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