Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators
文献类型：期刊论文
| 作者 | Du, Zidong1; Lingamneni, Avinash2; Chen, Yunji1,3; Palem, Krishna V.2; Temam, Olivier; Wu, Chengyong1 |
| 刊名 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
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| 出版日期 | 2015-08-01 |
| 卷号 | 34期号:8页码:1223-1235 |
| 关键词 | Accelerator architectures energy efficient hardware neuron network inexact computing |
| ISSN号 | 0278-0070 |
| DOI | 10.1109/TCAD.2015.2419628 |
| 英文摘要 | In recent years, inexact computing has been increasingly regarded as one of the most promising approaches for slashing energy consumption in many applications that can tolerate a certain degree of inaccuracy. Driven by the principle of trading tolerable amounts of application accuracy in return for significant resource savings-the energy consumed, the (critical path) delay, and the (silicon) area-this approach has been limited to application-specified integrated circuits (ASICs) so far. These ASIC realizations have a narrow application scope and are often rigid in their tolerance to inaccuracy, as currently designed; the latter often determining the extent of resource savings we would achieve. In this paper, we propose to improve the application scope, error resilience and the energy savings of inexact computing by combining it with hardware neural networks. These neural networks are fast emerging as popular candidate accelerators for future heterogeneous multicore platforms and have flexible error resilience limits owing to their ability to be trained. Our results in 65-nm technology demonstrate that the proposed inexact neural network accelerator could achieve 1.78-2.67x savings in energy consumption (with corresponding delay and area savings being 1.23 and 1.46x, respectively) when compared to the existing baseline neural network implementation, at the cost of a small accuracy loss (mean squared error increases from 0.14 to 0.20 on average). |
| 资助项目 | NSF of China[61100163] ; NSF of China[61133004] ; NSF of China[61222204] ; NSF of China[61221062] ; NSF of China[61303158] ; NSF of China[61432016] ; NSF of China[61472396] ; NSF of China[61473275] ; NSF of China[60921002] ; 973 Program of China[2015CB358800] ; 973 Program of China[2011CB302504] ; Strategic Priority Research Program of the CAS[XDA06010403] ; Strategic Priority Research Program of the CAS[XDB02040009] ; International Collaboration Key Program of the CAS[171111KYSB20130002] ; 10 000 Talent Program |
| WOS研究方向 | Computer Science ; Engineering |
| 语种 | 英语 |
| WOS记录号 | WOS:000358620700002 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/9463]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Du, Zidong |
| 作者单位 | 1.Chinese Acad Sci, State Key Lab Comp Architecture, Inst Comp Technol, Beijing 100190, Peoples R China 2.Rice Univ, Dept Elect & Comp Engn, Houston, TX 77005 USA 3.Chinese Acad Sci, CAS Ctr Excellence Brain Sci, Beijing 100190, Peoples R China |
| 推荐引用方式 GB/T 7714 | Du, Zidong,Lingamneni, Avinash,Chen, Yunji,et al. Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2015,34(8):1223-1235. |
| APA | Du, Zidong,Lingamneni, Avinash,Chen, Yunji,Palem, Krishna V.,Temam, Olivier,&Wu, Chengyong.(2015).Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,34(8),1223-1235. |
| MLA | Du, Zidong,et al."Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 34.8(2015):1223-1235. |
入库方式： OAI收割
来源：计算技术研究所
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