Microarchitecture of the Godson-2 processor
文献类型：期刊论文
| 作者 | Hu, WW; Zhang, FX; Li, ZS |
| 刊名 | JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
 |
| 出版日期 | 2005-03-01 |
| 卷号 | 20期号:2页码:243-249 |
| 关键词 | superscalar pipeline out-of-order execution branch prediction register renaming dynamic scheduling non-blocking cache load speculation |
| ISSN号 | 1000-9000 |
| 英文摘要 | The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18 mu m CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3 ns. |
| WOS研究方向 | Computer Science |
| 语种 | 英语 |
| WOS记录号 | WOS:000227919000013 |
| 出版者 | SCIENCE CHINA PRESS |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/10180]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Hu, WW |
| 作者单位 | Chinese Acad Sci, Comp Technol Inst, Beijing 100080, Peoples R China |
| 推荐引用方式 GB/T 7714 | Hu, WW,Zhang, FX,Li, ZS. Microarchitecture of the Godson-2 processor[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2005,20(2):243-249. |
| APA | Hu, WW,Zhang, FX,&Li, ZS.(2005).Microarchitecture of the Godson-2 processor.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,20(2),243-249. |
| MLA | Hu, WW,et al."Microarchitecture of the Godson-2 processor".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 20.2(2005):243-249. |
入库方式： OAI收割
来源：计算技术研究所
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