An efficient VLSI architecture for motion compensation of AVS HDTV decoder
文献类型：期刊论文
| 作者 | Zheng, Jun-Hao; Deng, Lei; Zhang, Peng; Xie, Don |
| 刊名 | JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
 |
| 出版日期 | 2006-05-01 |
| 卷号 | 21期号:3页码:370-377 |
| 关键词 | motion compensation AVS VLSI architecture |
| ISSN号 | 1000-9000 |
| 英文摘要 | In the part 2 of advanced Audio Video coding Standard (AVS-P2), many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, symmetric matching, quarter precision interpolation, etc. However, these new features enormously increase the computational complexity and the memory bandwidth requirement, which make motion compensation a difficult component in the implementation of the AVS HDTV decoder. This paper proposes an efficient motion compensation architecture for AVS-P2 video standard up to the Level 6.2 of the Jizhun Profile. It has a macroblock-level pipelined structure which consists of MV predictor unit, reference fetch unit and pixel interpolation unit. The proposed architecture exploits the parallelism in the AVS motion compensation algorithm to accelerate the speed of operations and uses the dedicated design to optimize the memory access. And it has been integrated in a prototype chip which is fabricated with TSMC 0.18-mu m CMOS technology, and the experimental results show that this architecture can achieve the real time AVS-P2 decoding for the HDTV 1080i (1920 X 1088 4 : 2 : 0 60field/s) video. The efficient design can work at the frequency of 148.5MHz and the total gate count is about 225K. |
| WOS研究方向 | Computer Science |
| 语种 | 英语 |
| WOS记录号 | WOS:000238079200011 |
| 出版者 | SCIENCE PRESS |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/10459]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Zheng, Jun-Hao |
| 作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China 2.Harbin Inst Technol, Dept Comp Sci, Harbin 150001, Peoples R China 3.Grad Univ, Chinese Acad Sci, Beijing 100039, Peoples R China 4.Grandview Semicond Beijing Corp, Beijing 100039, Peoples R China |
| 推荐引用方式 GB/T 7714 | Zheng, Jun-Hao,Deng, Lei,Zhang, Peng,et al. An efficient VLSI architecture for motion compensation of AVS HDTV decoder[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2006,21(3):370-377. |
| APA | Zheng, Jun-Hao,Deng, Lei,Zhang, Peng,&Xie, Don.(2006).An efficient VLSI architecture for motion compensation of AVS HDTV decoder.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,21(3),370-377. |
| MLA | Zheng, Jun-Hao,et al."An efficient VLSI architecture for motion compensation of AVS HDTV decoder".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 21.3(2006):370-377. |
入库方式： OAI收割
来源：计算技术研究所
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