An efficient VLSI architecture of VLD for AVS HDTV decoder
文献类型：期刊论文
| 作者 | Sheng, Bin; Gao, Wen; Xie, Don; Wu, Di |
| 刊名 | IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
 |
| 出版日期 | 2006-05-01 |
| 卷号 | 52期号:2页码:696-701 |
| 关键词 | Variable Length Code Decoder AVS video decoder VLSI |
| ISSN号 | 0098-3063 |
| 英文摘要 | In this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-Golomb Code, and AVS 2-D Variable Length Code. Furthermore, it has a preprocessing. submodule, which can perform Start Code Detection and De-stuffing for the input bitstream. The proposed architecture. has been described in Verilog HDL, simulated with VCS digital simulator, and implemented using 0.18 mu m Artisan CMOS cells library by Synopsys Design Compiler. The circuit costs about 15k equivalent logic gates (not including 4kb on-chip SRAY). And the critical path is less than 6ns in the worst case. This design has been implemented in a single chip AVS HDTV decoder, AVS101, Which can support real-time decoding for NTSC, PAL, 60 frames/s or 1080i 60 fields/s programs. Although the architecture was originally designed for AVS. video standard, it can be easily adapted to other coding standards. |
| WOS研究方向 | Engineering ; Telecommunications |
| 语种 | 英语 |
| WOS记录号 | WOS:000238870000059 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/10666]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Sheng, Bin |
| 作者单位 | 1.Harbin Inst Technol, Dept Comp Sci & Engn, Harbin 150006, Peoples R China 2.Chinese Acad Sci, Comp Technol Inst, Beijing 100864, Peoples R China |
| 推荐引用方式 GB/T 7714 | Sheng, Bin,Gao, Wen,Xie, Don,et al. An efficient VLSI architecture of VLD for AVS HDTV decoder[J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,2006,52(2):696-701. |
| APA | Sheng, Bin,Gao, Wen,Xie, Don,&Wu, Di.(2006).An efficient VLSI architecture of VLD for AVS HDTV decoder.IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,52(2),696-701. |
| MLA | Sheng, Bin,et al."An efficient VLSI architecture of VLD for AVS HDTV decoder".IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 52.2(2006):696-701. |
入库方式： OAI收割
来源：计算技术研究所
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