Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology
文献类型：期刊论文
| 作者 | Hu, Wei-Wu; Zhao, Ji-Ye; Zhong, Shi-Qiang; Yang, Xu; Guidetti, Elio; Wu, Chris |
| 刊名 | JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
 |
| 出版日期 | 2007 |
| 卷号 | 22期号:1页码:1-14 |
| 关键词 | general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design synthesis flow bit-sliced placement crafted cell performance evaluation |
| ISSN号 | 1000-9000 |
| 英文摘要 | This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bit-sliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500. |
| WOS研究方向 | Computer Science |
| 语种 | 英语 |
| WOS记录号 | WOS:000243890200001 |
| 出版者 | SCIENCE CHINA PRESS |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/11061]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Hu, Wei-Wu |
| 作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100080, Peoples R China 2.ST Microelectron, Geneva, Switzerland |
| 推荐引用方式 GB/T 7714 | Hu, Wei-Wu,Zhao, Ji-Ye,Zhong, Shi-Qiang,et al. Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2007,22(1):1-14. |
| APA | Hu, Wei-Wu,Zhao, Ji-Ye,Zhong, Shi-Qiang,Yang, Xu,Guidetti, Elio,&Wu, Chris.(2007).Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,22(1),1-14. |
| MLA | Hu, Wei-Wu,et al."Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 22.1(2007):1-14. |
入库方式： OAI收割
来源：计算技术研究所
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