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Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling

文献类型：期刊论文

作者Dong, Jianbo1,2; Zhang, Lei2; Han, Yinhe1,2; Yan, Guihai1,2; Li, Xiaowei1,2
刊名JOURNAL OF SYSTEMS ARCHITECTURE
出版日期2010-10-01
卷号56期号:10页码:534-542
关键词Process variation Thread-level redundancy Chip Multiprocessor Scheduling
ISSN号1383-7621
DOI10.1016/j.sysarc.2010.09.003
英文摘要Thread-level redundancy is an efficient approach for transient fault detection and recovery in Chip Multiprocessors (CMPs), in which two adjacent cores are statically coupled to form a functional Dual Modular Redundancy (DMR). Manufacturing process variations cause core-to-core (C2C) performance asymmetry across the chip, which can be further divided into the asymmetry among core-pairs and the asymmetry within a core-pair. We call them inter- and intra-pair asymmetries, respectively, both of which should be taken into considerations in application scheduling for CMPs with static core coupling. In this paper, we first formulate the above scheduling problem as a 0-1 programming problem to maximize the system Weighted Throughput. An efficient IVF&AppSen algorithm is then proposed, which we prove to be optimal when the number of applications equals to that of core-pairs. We also adapt the Simulated Annealing technique to tackle this problem when applications are less than core-pairs on chip. Simulations on a 64-core CMP shows that the proposed algorithms achieve 2.5-9.3% improvement in Weighted Throughput when compared to prior VarF&AppIPC algorithm. (C) 2010 Elsevier B.V. All rights reserved.
资助项目National Basic Research Program of China (973)[2011CB302503] ; National Natural Science Foundation of China (NSFC)[60806014] ; National Natural Science Foundation of China (NSFC)[60831160526] ; National Natural Science Foundation of China (NSFC)[60633060] ; National Natural Science Foundation of China (NSFC)[60921002] ; National Natural Science Foundation of China (NSFC)[61076037] ; National Natural Science Foundation of China (NSFC)[60906018] ; Hi-Tech Research and Development Program of China (863)[2009AA01Z126]
WOS研究方向Computer Science
语种英语
WOS记录号WOS:000284570600005
出版者ELSEVIER SCIENCE BV
源URL[http://119.78.100.204/handle/2XEOYT63/12299]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Han, Yinhe
作者单位1.Chinese Acad Sci, Grad Univ, Beijing, Peoples R China
2.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing, Peoples R China
推荐引用方式
GB/T 7714		 Dong, Jianbo,Zhang, Lei,Han, Yinhe,et al. Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling[J]. JOURNAL OF SYSTEMS ARCHITECTURE,2010,56(10):534-542.
APA Dong, Jianbo,Zhang, Lei,Han, Yinhe,Yan, Guihai,&Li, Xiaowei.(2010).Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.JOURNAL OF SYSTEMS ARCHITECTURE,56(10),534-542.
MLA Dong, Jianbo,et al."Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling".JOURNAL OF SYSTEMS ARCHITECTURE 56.10(2010):534-542.

入库方式： OAI收割

来源：计算技术研究所

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