Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects
文献类型：期刊论文
| 作者 | Zhang, Ying; Li, Huawei; Min, Yinghua; Li, Xiaowei |
| 刊名 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
 |
| 出版日期 | 2011-10-01 |
| 卷号 | 19期号:10页码:1787-1800 |
| 关键词 | Crosstalk crosstalk tolerance interconnects network-on-chip (NOC) |
| ISSN号 | 1063-8210 |
| DOI | 10.1109/TVLSI.2010.2062201 |
| 英文摘要 | With the shrink of technology to the nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting many cores on a single chip. It suffers however from increasingly serious interconnect crosstalk effects, which constrain the overall performance of NOC systems. In this paper, a crosstalk tolerance method is proposed for reducing bus delay on NOC interconnects. Crosstalk-induced latency is predicted by analyzing the possible crosstalk effects of adjacent patterns stored in an NOC router. Transition times of selected bits are then adjusted to relieve these predicted crosstalk-induced effects. Experimental results on interconnects show that the proposed method can achieve the same bus delay reduction as the insertion of extra shielding wires into two adjacent wires, while the proposed method requires no extra wires. Compared with previous methods using a dual rail code, a crosstalk avoidance code, and/or a variable clock, the proposed approach provides a larger reduction of bus delay with less area overhead. |
| 资助项目 | National Natural Science Foundation of China (NSFC)[60776031] ; National Natural Science Foundation of China (NSFC)[60633060] ; National Natural Science Foundation of China (NSFC)[60921002] ; National Basic Research Program of China (973)[2005CB321605] |
| WOS研究方向 | Computer Science ; Engineering |
| 语种 | 英语 |
| WOS记录号 | WOS:000293755900006 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/12532]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Zhang, Ying |
| 作者单位 | Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100190, Peoples R China |
| 推荐引用方式 GB/T 7714 | Zhang, Ying,Li, Huawei,Min, Yinghua,et al. Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2011,19(10):1787-1800. |
| APA | Zhang, Ying,Li, Huawei,Min, Yinghua,&Li, Xiaowei.(2011).Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,19(10),1787-1800. |
| MLA | Zhang, Ying,et al."Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 19.10(2011):1787-1800. |
入库方式： OAI收割
来源：计算技术研究所
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