The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications
文献类型：期刊论文
| 作者 | Luo, ZY; Min, YH; Yang, SY; Li, XW |
| 刊名 | SCIENCE IN CHINA SERIES F
 |
| 出版日期 | 2002-12-01 |
| 卷号 | 45期号:6页码:401-415 |
| 关键词 | CMOS VLSI power estimation test power |
| ISSN号 | 1009-2757 |
| 英文摘要 | The authors theoretically describe the monotonic increasing relationship between average powers of a CMOS VLSI circuit with and without delay. The power of an ideal circuit without delay, which can be fast computed, has been used as the evaluation criterion for the power of a practical circuit with delay, which needs more computing time, in such fields as fast estimation for the average power and the maximum power, and fast optimization for the low test power. The authors propose a novel simulation approach that uses delay-free power to compact a long input vector pair sequence into a short sequence and then, uses the compacted one to fast simulate the average (or maximum) power for a CMOS circuit. In comparison with the traditional simulation approach that uses an un-compacted input sequence to simulate the average (or maximum) power, experiment results demonstrate that in the field of fast estimation for the average power, the present approach can be 6-10 times faster without significant loss in accuracy (less than 3.5% on average), and in the field of fast estimation for the maximum power, this approach can be 6-8 times faster without significant loss in accuracy (less than 5% on average). In the field of fast optimization for the test power, the authors propose a novel delay-free power optimization approach for the test power. Experiment results demonstrate that, in comparison with the approach of direct optimization and the approach of Hamming distance optimization, this approach is of the highest optimization efficiency because it needs shorter time (16.84%) to obtain a better optimization effect (reducing 35.11% test power). |
| WOS研究方向 | Computer Science |
| 语种 | 英语 |
| WOS记录号 | WOS:000179596300001 |
| 出版者 | SCIENCE CHINA PRESS |
| 源URL | [http://119.78.100.204/handle/2XEOYT63/13574]  |
| 专题 | 中国科学院计算技术研究所期刊论文_英文 |
| 通讯作者 | Luo, ZY |
| 作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China 2.Tsing Hua Univ, Dept Automat, Beijing 100084, Peoples R China |
| 推荐引用方式 GB/T 7714 | Luo, ZY,Min, YH,Yang, SY,et al. The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications[J]. SCIENCE IN CHINA SERIES F,2002,45(6):401-415. |
| APA | Luo, ZY,Min, YH,Yang, SY,&Li, XW.(2002).The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications.SCIENCE IN CHINA SERIES F,45(6),401-415. |
| MLA | Luo, ZY,et al."The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications".SCIENCE IN CHINA SERIES F 45.6(2002):401-415. |
入库方式： OAI收割
来源：计算技术研究所
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