中国科学院机构知识库网格
Chinese Academy of Sciences Institutional Repositories Grid
Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

文献类型:期刊论文

作者Wu, QQ ; Chen, J ; Lu, ZC ; Zhou, ZM ; Luo, JX ; Chai, Z ; Yu, T ; Qiu, C ; Li, L ; Pang, A ; Wang, X ; Fossum, JG
刊名IEEE ELECTRON DEVICE LETTERS
出版日期2012
卷号33期号:6页码:743-745
关键词Capacitorless DRAM overlap SOI floating-body cell (FBC) tunneling field-effect transistor (T-FET) underlap
ISSN号0741-3106
通讯作者Wu, QQ (reprint author), Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat, Shanghai 200050, Peoples R China.
中文摘要A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case re
学科主题Engineering
收录类别2012SCI-108
原文出处10.1109/LED.2012.2190031
语种英语
公开日期2013-04-17
源URL[http://ir.sim.ac.cn/handle/331004/114767]  
专题上海微系统与信息技术研究所_功能材料与器件_期刊论文
推荐引用方式
GB/T 7714
Wu, QQ,Chen, J,Lu, ZC,et al. Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories[J]. IEEE ELECTRON DEVICE LETTERS,2012,33(6):743-745.
APA Wu, QQ.,Chen, J.,Lu, ZC.,Zhou, ZM.,Luo, JX.,...&Fossum, JG.(2012).Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories.IEEE ELECTRON DEVICE LETTERS,33(6),743-745.
MLA Wu, QQ,et al."Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories".IEEE ELECTRON DEVICE LETTERS 33.6(2012):743-745.

入库方式: OAI收割

来源:上海微系统与信息技术研究所

浏览0
下载0
收藏0
其他版本

除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。