A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector
文献类型：会议论文
| 作者 | Liu, SL ; Hao, ZK ; Ma, HP ; Yuan, L ; Shi, Y |
| 出版日期 | 2008 |
| 会议名称 | 9th international conference on solid-state and integrated-circuit technology |
| 会议日期 | oct 20-23, 2008 |
| 会议地点 | beijing, peoples r china |
| 关键词 | PLL |
| 页码 | vols 1-4: 1996-1999 |
| 通讯作者 | liu, sl, chinese acad sci, inst semicond, beijing 100083, peoples r china. |
| 中文摘要 | a seven-state phase frequency detector (s.s pfd) is proposed for fast-locking charge pump based phase-locked loops (cpplls) in this paper. the locking time of the pll can be significantly reduced by using the seven-state pfd to inject more current into the loop filter. in this stage, the bandwidth of the pll is increased or decreased to track the phase difference of the reference signal and the feedback signal. the proposed architecture is realized in a standard 0.35 mu m 2p4m cmos process with a 3.3v supply voltage. the locking time of the proposed pll is 1.102 mu s compared with the 2.347 mu s of the pll based on continuous-time pfd and the 3.298 mu s of the pll based on the pass-transistor tri-state pfd. there are 53.05% and 66.59% reductions of the locking time. the simulation results and the comparison with other plls demonstrate that the proposed seven-state pfd is effective to reduce locking time. |
| 英文摘要 | a seven-state phase frequency detector (s.s pfd) is proposed for fast-locking charge pump based phase-locked loops (cpplls) in this paper. the locking time of the pll can be significantly reduced by using the seven-state pfd to inject more current into the loop filter. in this stage, the bandwidth of the pll is increased or decreased to track the phase difference of the reference signal and the feedback signal. the proposed architecture is realized in a standard 0.35 mu m 2p4m cmos process with a 3.3v supply voltage. the locking time of the proposed pll is 1.102 mu s compared with the 2.347 mu s of the pll based on continuous-time pfd and the 3.298 mu s of the pll based on the pass-transistor tri-state pfd. there are 53.05% and 66.59% reductions of the locking time. the simulation results and the comparison with other plls demonstrate that the proposed seven-state pfd is effective to reduce locking time.; zhangdi于2010-03-09批量导入; made available in dspace on 2010-03-09t07:08:16z (gmt). no. of bitstreams: 1 287.pdf: 1006946 bytes, checksum: ed2e8f82b532609d6572c1c2f4467331 (md5) previous issue date: 2008; ieee beijing sect.; chinese inst elect.; ieee electron devices soc.; ieee eds beijing chapter.; ieee solid state circuits soc.; ieee circuites & syst soc.; ieee hong kong eds, sscs chapter.; ieee sscs beijing chapter.; japan soc appl phys.; elect div ieee.; ursi commiss d.; inst elect engineers korea.; assoc asia pacific phys soc.; peking univ, ieee eds student chapter.; [liu, silin; hao, zhikun; ma, heping; yuan, ling; shi, yin] chinese acad sci, inst semicond, beijing 100083, peoples r china |
| 收录类别 | CPCI-S |
| 会议主办者 | ieee beijing sect.; chinese inst elect.; ieee electron devices soc.; ieee eds beijing chapter.; ieee solid state circuits soc.; ieee circuites & syst soc.; ieee hong kong eds, sscs chapter.; ieee sscs beijing chapter.; japan soc appl phys.; elect div ieee.; ursi commiss d.; inst elect engineers korea.; assoc asia pacific phys soc.; peking univ, ieee eds student chapter. |
| 会议录 | 2008 9th international conference on solid-state and integrated-circuit technology
 |
| 会议录出版者 | ieee ; 345 e 47th st, new york, ny 10017 usa |
| 学科主题 | 微电子学 |
| 会议录出版地 | 345 e 47th st, new york, ny 10017 usa |
| 语种 | 英语 |
| ISBN号 | 978-1-4244-2185-5 |
| 源URL | [http://ir.semi.ac.cn/handle/172111/8300]  |
| 专题 | 半导体研究所_中国科学院半导体研究所（2009年前） |
| 推荐引用方式 GB/T 7714 | Liu, SL,Hao, ZK,Ma, HP,et al. A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector[C]. 见:9th international conference on solid-state and integrated-circuit technology. beijing, peoples r china. oct 20-23, 2008. |
入库方式： OAI收割
来源：半导体研究所
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