Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization
文献类型：会议论文
| 作者 | Chen XB
|
| 出版日期 | 2005 |
| 会议名称 | conference on optical transmission, switching and subsystems ii |
| 会议日期 | nov 09-11, 2004 |
| 会议地点 | beijing, peoples r china |
| 关键词 | VSR |
| 页码 | pts 1 and 2 5625: 933-937 part 1-2 |
| 通讯作者 | zhou, y, chinese acad sci, inst semicond, state key lab integrated optoelect, beijing 100083, peoples r china. |
| 中文摘要 | this paper proposes a novel and innovative scheme for 10gb/s parallel very short reach (vsr) optical communication system. the optimized scheme properly manages the sdh/sonet redundant bytes and adjusts the position of error detecting bytes and error correction bytes. compared with the oif-vsr4-01.0 proposal, the scheme has a coding process module. the sdh/sonet frames in transmission direction are disposed as follows: (1) the framer-serdes interface (fsi) gets 16x622.08mb/s stm-64 frame. (2) the stm-64 frame is byte-wise stripped across 12 channels, all channels are data channels. during this process, the parity bytes and crc bytes are generated in the similar way as oif-vsr4-01.0 and stored in the code process module. (3) the code process module will regularly convey the additional parity bytes and crc bytes to all 12 data channels. (4) after the 8b/10b coding, the 12 channels is transmitted to the parallel vcsel array. the receive process approximately in reverse order of transmission process. by applying this scheme to 10gb/s vsr system, the frame size in vsr system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously. |
| 英文摘要 | this paper proposes a novel and innovative scheme for 10gb/s parallel very short reach (vsr) optical communication system. the optimized scheme properly manages the sdh/sonet redundant bytes and adjusts the position of error detecting bytes and error correction bytes. compared with the oif-vsr4-01.0 proposal, the scheme has a coding process module. the sdh/sonet frames in transmission direction are disposed as follows: (1) the framer-serdes interface (fsi) gets 16x622.08mb/s stm-64 frame. (2) the stm-64 frame is byte-wise stripped across 12 channels, all channels are data channels. during this process, the parity bytes and crc bytes are generated in the similar way as oif-vsr4-01.0 and stored in the code process module. (3) the code process module will regularly convey the additional parity bytes and crc bytes to all 12 data channels. (4) after the 8b/10b coding, the 12 channels is transmitted to the parallel vcsel array. the receive process approximately in reverse order of transmission process. by applying this scheme to 10gb/s vsr system, the frame size in vsr system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.; zhangdi于2010-03-29批量导入; zhangdi于2010-03-29批量导入; spie.; chinese opt soc.; china inst commun.; chinese acad sci, inst semicond, state key lab integrated optoelect, beijing 100083, peoples r china |
| 收录类别 | 其他 |
| 会议主办者 | spie.; chinese opt soc.; china inst commun. |
| 会议录 | optical transmission switching and subsystem ii丛书标题: proceedings of the society of photo-optical instrumentation engineers (spie)
 |
| 会议录出版者 | spie-int soc optical engineering ; 1000 20th st, po box 10, bellingham, wa 98227-0010 usa |
| 学科主题 | 光电子学 |
| 会议录出版地 | 1000 20th st, po box 10, bellingham, wa 98227-0010 usa |
| 语种 | 英语 |
| ISSN号 | 0277-786x |
| ISBN号 | 0-8194-5579-2 |
| 源URL | [http://ir.semi.ac.cn/handle/172111/10116]  |
| 专题 | 半导体研究所_中国科学院半导体研究所（2009年前） |
| 推荐引用方式 GB/T 7714 | Chen XB. Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization[C]. 见:conference on optical transmission, switching and subsystems ii. beijing, peoples r china. nov 09-11, 2004. |
入库方式： OAI收割
来源：半导体研究所
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