A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation
文献类型：会议论文
| 作者 | Li YJ (Li Yuan-Jin) ; Zhang WC (Zhang WanCheng) ; Wu NJ (Wu Nan-Jian) |
| 出版日期 | 2009 |
| 会议名称 | 2009 ieee 8th international conference on asic |
| 会议日期 | 2009 |
| 会议地点 | changsha, peoples r china |
| 关键词 | Vision Chip Safety Driving Assist Lane Detection Dual-Core Processing Element Array |
| 页码 | 917-920 |
| 通讯作者 | li, yj, chinese acad sci, inst semicond, state key lab superlattices & microstruct, beijing 100083, peoples r china. e-mail address: nanjian@red.semi.ac.cn |
| 英文摘要 | this paper presents a novel architecture of vision chip for fast traffic lane detection (ftld). the architecture consists of a 32*32 simd processing element (pe) array processor and a dual-core risc processor. the pe array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without i/o bottleneck. the dual-core processor carries out high-level image processing. a parallel fast lane detection algorithm for this architecture is developed. the fpga system with a cmos image sensor is used to implement the architecture. experiment results show that the system can perform the fast traffic lane detection at 50fps rate. it is much faster than previous works and has good robustness that can operate in various intensity of light. the novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.; submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-04-13t02:59:28z no. of bitstreams: 1 a novel architecture of vision chip for fast traffic lane detection and fpga implementation.pdf: 9576536 bytes, checksum: 5b0e756cbabd4968f16dd05f6f076d30 (md5); made available in dspace on 2010-04-13t02:59:28z (gmt). no. of bitstreams: 1 a novel architecture of vision chip for fast traffic lane detection and fpga implementation.pdf: 9576536 bytes, checksum: 5b0e756cbabd4968f16dd05f6f076d30 (md5) previous issue date: 2009; ieee beijing sect.; fudan univ.; ieee china council.; natl univ def tech.; ieee cas, ieee sscs.; chinese inst elect.; 其它 |
| 收录类别 | CPCI（ISTP） |
| 合作状况 | 其它 |
| 会议主办者 | ieee beijing sect.; fudan univ.; ieee china council.; natl univ def tech.; ieee cas, ieee sscs.; chinese inst elect. |
| 会议录 | 2009 ieee 8th international conference on asic
 |
| 会议录出版者 | ieee ; 345 e 47th st, new york, ny 10017 usa |
| 学科主题 | 微电子学 |
| 会议录出版地 | 345 e 47th st, new york, ny 10017 usa |
| 语种 | 英语 |
| ISBN号 | 978-1-4244-3868-6 |
| 源URL | [http://ir.semi.ac.cn/handle/172111/11145]  |
| 专题 | 半导体研究所_中国科学院半导体研究所（2009年前） |
| 推荐引用方式 GB/T 7714 | Li YJ ,Zhang WC ,Wu NJ . A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation[C]. 见:2009 ieee 8th international conference on asic. changsha, peoples r china. 2009. |
入库方式： OAI收割
来源：半导体研究所
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