Submount, pedestal, and bond wire assembly for a transistor outline package with reduced bond wire inductance
文献类型：专利
| 作者 | GIARETTA, GIORGIO; NGUYEN, THE' LING; LIPSON, JAN; HOFMEISTER, RUDOLF J. |
| 发表日期 | 2003-11-27 |
| 专利号 | US20030218923A1 |
| 著作权人 | FINISAR CORPORATION |
| 国家 | 美国 |
| 文献子类 | 发明申请 |
| 其他题名 | Submount, pedestal, and bond wire assembly for a transistor outline package with reduced bond wire inductance |
| 英文摘要 | The present invention relates generally to optoelectronic devices, and particularly to a submount, pedestal, and bond wire assembly for a transistor outline package. A bottom surface of the submount is connected to a top surface of the pedestal. Each bond wire in a bond wire set is connected to a position on the top surface of the submount, and to a position on the signal line. The signal line is positioned a first distance from the position on the top surface of the submount and a second distance from the pedestal. The submount is sized such that a portion of the bottom and the top surface of the submount extends beyond the top surface of the pedestal such that the first distance is less than the second distance. |
| 公开日期 | 2003-11-27 |
| 申请日期 | 2003-03-19 |
| 状态 | 授权 |
| 源URL | [http://ir.opt.ac.cn/handle/181661/60943]  |
| 专题 | 半导体激光器专利数据库 |
| 作者单位 | FINISAR CORPORATION |
| 推荐引用方式 GB/T 7714 | GIARETTA, GIORGIO,NGUYEN, THE' LING,LIPSON, JAN,et al. Submount, pedestal, and bond wire assembly for a transistor outline package with reduced bond wire inductance. US20030218923A1. 2003-11-27. |
入库方式： OAI收割
来源：西安光学精密机械研究所
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