A 14-bit column-parallel two-step SA ADC with digital calibration based on scaled references and redundancy for CMOS image sensors
文献类型：期刊论文
| 作者 | Li Zhelu; Xie Ning; Fan Wei; Xi Jianxiong; He Lenian; Sun Kexu |
| 刊名 | ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
 |
| 出版日期 | 2019 |
| 卷号 | 100期号:2页码:295-309 |
| 关键词 | SA ADC Scaled-reference Redundancy Calibration CIS |
| DOI | 10.1007/s10470-018-1368-1 |
| 英文摘要 | A 14-bit column-parallel two-step successive approximation (SA) analog-to-digital converter (ADC) with digital calibration based on scaled references and redundancy for CMOS image sensors is presented. A 7-bit area-efficient non-binary capacitor array whose total number is same as the 6-bit one is used to meet the dimension constraints imposed by the pixel pitch of 25 mu m in the CMOS image sensor. In each conversion period, 14-bit resolution is realized by 16-times comparison which provides redundancy for calibration. Capacitor mismatch and scaled-reference error both deviate the weight of each bit from its designed value. An off-chip digital calibration method based on statistics is adopted to extract the fabricated weight of each bit in the SA ADC. A tri-level switching scheme is employed for the most 8 significant times comparison to reduce switching power of the capacitor array of the SA ADC. The proposed SA ADC is implemented by using 180 nm CIS process and measured at 1 MS/s. The area of the SA ADC is 1637 x 50 mu m(2). It consumes 78.47 mu A under 3.3 V supply voltage. The INL is improved from + 21/- 21 to + 2.3/- 2.5 LSB, SFDR from 73.56 to 85.17 dB and ENOB from 9.57 to 11.15 bit after calibration in the presence of capacitor mismatch and scaled reference errors. The figure of merit of the ADC is 118 fJ/Conv.-step. |
| WOS记录号 | WOS:476531100007 |
| 源URL | [http://202.127.2.71:8080/handle/181331/12364]  |
| 专题 | 上海技术物理研究所_上海技物所 |
| 推荐引用方式 GB/T 7714 | Li Zhelu,Xie Ning,Fan Wei,et al. A 14-bit column-parallel two-step SA ADC with digital calibration based on scaled references and redundancy for CMOS image sensors[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING,2019,100(2):295-309. |
| APA | Li Zhelu,Xie Ning,Fan Wei,Xi Jianxiong,He Lenian,&Sun Kexu.(2019).A 14-bit column-parallel two-step SA ADC with digital calibration based on scaled references and redundancy for CMOS image sensors.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING,100(2),295-309. |
| MLA | Li Zhelu,et al."A 14-bit column-parallel two-step SA ADC with digital calibration based on scaled references and redundancy for CMOS image sensors".ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 100.2(2019):295-309. |
入库方式： OAI收割
来源：上海技术物理研究所
浏览0
下载0
收藏0
其他版本
除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。