A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs
文献类型：期刊论文
| 作者 | Jiao, Y.2; Zhang, Q.1; Chen, W.2; Zhou, L.2; Chen, C.2
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| 刊名 | JOURNAL OF INSTRUMENTATION
 |
| 出版日期 | 2021 |
| 卷号 | 16 |
| ISSN号 | 1748-0221 |
| 关键词 | Digital electronic circuits Front-end electronics for detector readout Data acquisition circuits, VLSI circuits |
| DOI | 10.1088/1748-0221/16/01/P01012 |
| 通讯作者 | Chen, C.(chench@ustc.edu.cn) |
| 英文摘要 | A resource-saving dual channel time-to-digital converter (TDC) in field programmable gate array (FPGA) is presented in this paper. The presented TDC is formed by cascading a channel waveform generator (CWG) and a tapped delay line. Specifically, the CWG can generate six types of waveforms with different transition edges to propagate on tapped delay line according to the different assertion times of two hit signals. Besides, a pipelined encoding module is designed to detect the positions of multiple transition edges on tapped delay line precisely so that the six types of waveforms can be identified and the two hit signals can be distinguished and measured. Since the measurements of two hit signals share one tapped delay line, the TDC based on CWG (CWG-TDC) is a resource-saving dual channel TDC. To evaluate the performance of CWG-TDC, time intervals from 10ns to 200ns were measured on a Xilinx's 40nm Virtex-6 development board. In CWG-TDC, channel 1 and channel 2 can achieve LSB of 9ps, the highest RMS precision of 6.2ps. The consistency between experimental results and theoretical analysis shows that the presented CWG-TDC can not only achieve high RMS precision but also achieve resource-saving. |
| WOS关键词 | OF-FLIGHT |
| 资助项目 | Natural Science Foundation of China[61971392] |
| WOS研究方向 | Instruments & Instrumentation |
| 语种 | 英语 |
| 出版者 | IOP PUBLISHING LTD |
| WOS记录号 | WOS:000663343100028 |
| 资助机构 | Natural Science Foundation of China |
| 源URL | [http://ir.hfcas.ac.cn:8080/handle/334002/123820]  |
| 专题 | 中国科学院合肥物质科学研究院 |
| 通讯作者 | Chen, C. |
| 作者单位 | 1.Chinese Acad Sci, HFIPS, Anhui Inst Opt & Fine Mech, Key Lab Opt Calibrat & Characterizat, Hefei 230031, Anhui, Peoples R China 2.Univ Sci & Technol China, Dept Elect Engn & Informat Sci, Hefei 230026, Anhui, Peoples R China |
| 推荐引用方式 GB/T 7714 | Jiao, Y.,Zhang, Q.,Chen, W.,et al. A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs[J]. JOURNAL OF INSTRUMENTATION,2021,16. |
| APA | Jiao, Y.,Zhang, Q.,Chen, W.,Zhou, L.,&Chen, C..(2021).A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs.JOURNAL OF INSTRUMENTATION,16. |
| MLA | Jiao, Y.,et al."A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs".JOURNAL OF INSTRUMENTATION 16(2021). |
入库方式： OAI收割
来源：合肥物质科学研究院
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