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Defect Analysis and Parallel Testing or 3D Hybrid CMOS-Memristor Memory

文献类型：期刊论文

作者Liu, Peng4; You, Zhiqiang3; Wu, Jigang4; Elimu, Michael3; Wang, Weizheng2; Cai, Shuo2; Han, Yinhe1
刊名IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
出版日期2021-04-01
卷号9期号:2页码:745-758
关键词Non-volatile memory RRAM CMOL memristor testing
ISSN号2168-6750
DOI10.1109/TETC.2020.2982830
英文摘要CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately 5n/4x and n x , respectively, where n is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DM' can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells.
资助项目State Key Laboratory of Computer Architecture (ICT, CAC)[CARCH201907] ; National Key R&D Program of China[2018YFB1003201] ; National Natural Science Foundation of China[61672171] ; National Natural Science Foundation of China[61702052] ; Major Research plan of the National Natural Science Foundation of China[91964108] ; Hunan Provincial Natural Science Foundation[2018JJ2064] ; Guangdong Natural Science Foundation[2018B030311007] ; Guangdong Key R&D Project of China[2016KZDXM052] ; Guangdong Key R&D Project of China[2018B010107003] ; Guangdong Key R&D Project of China[2019B010118001]
WOS研究方向Computer Science ; Telecommunications
语种英语
WOS记录号WOS:000658346300016
出版者IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
源URL[http://119.78.100.204/handle/2XEOYT63/17608]  
专题中国科学院计算技术研究所期刊论文_英文
通讯作者You, Zhiqiang; Wu, Jigang
作者单位1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
2.Changsha Univ Sci & Technol, Coll Comp & Commun Engn, Changsha 410114, Peoples R China
3.Hunan Univ, Coll Comp Sci & Elect Engn, Key Lab Embedded & Network Comp Hunan Prov, Changsha 410082, Peoples R China
4.Guangdong Univ Technol, Sch Comp, Guangzhou 510006, Peoples R China
推荐引用方式
GB/T 7714		 Liu, Peng,You, Zhiqiang,Wu, Jigang,et al. Defect Analysis and Parallel Testing or 3D Hybrid CMOS-Memristor Memory[J]. IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING,2021,9(2):745-758.
APA Liu, Peng.,You, Zhiqiang.,Wu, Jigang.,Elimu, Michael.,Wang, Weizheng.,...&Han, Yinhe.(2021).Defect Analysis and Parallel Testing or 3D Hybrid CMOS-Memristor Memory.IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING,9(2),745-758.
MLA Liu, Peng,et al."Defect Analysis and Parallel Testing or 3D Hybrid CMOS-Memristor Memory".IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 9.2(2021):745-758.

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