A low dead time vernier delay line TDC implemented in an actel flash-based FPGA
文献类型:期刊论文
作者 | Qin Xi2; Feng Changqing2; Zhang Deliang2; Zhao Lei2; Liu Shubin2; An Qi2 |
刊名 | NUCLEAR SCIENCE AND TECHNIQUES
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出版日期 | 2013 |
卷号 | 24期号:4 |
关键词 | TO-DIGITAL CONVERTER PROGRAMMABLE-GATE-ARRAYS RESOLUTION SYSTEM Time measurement Vernier Time-to-digital convertor Double delay lines Compensation |
ISSN号 | 1001-8042 |
其他题名 | A low dead time vernier delay line TDC implemented in an actel flash-based FPGA |
英文摘要 | In this paper, a high precision vernier delay line (VDL) TDC (Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented, achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size. The TDC has a dead time of about 200 ns while the dynamic range is 655.36 vs. The double delay lines method is employed to cut the dead time in half to improve its performance. As the bin size of the TDC is dependent on temperature, a compensation algorithm is adopted as temperature drift correction, and the TDC shows satisfying performance in a temperature range from -5 degrees C to +55 degrees C. |
资助项目 | [State Key Program of National Natural Science of China] ; [Fundamental Research Funds for the Central Universities] |
语种 | 英语 |
CSCD记录号 | CSCD:4930153 |
源URL | [http://119.78.100.186/handle/113462/139089] ![]() |
专题 | 中国科学院近代物理研究所 |
作者单位 | 1.中国科学院近代物理研究所 2.中国科学院高能物理研究所 |
推荐引用方式 GB/T 7714 | Qin Xi,Feng Changqing,Zhang Deliang,et al. A low dead time vernier delay line TDC implemented in an actel flash-based FPGA[J]. NUCLEAR SCIENCE AND TECHNIQUES,2013,24(4). |
APA | Qin Xi,Feng Changqing,Zhang Deliang,Zhao Lei,Liu Shubin,&An Qi.(2013).A low dead time vernier delay line TDC implemented in an actel flash-based FPGA.NUCLEAR SCIENCE AND TECHNIQUES,24(4). |
MLA | Qin Xi,et al."A low dead time vernier delay line TDC implemented in an actel flash-based FPGA".NUCLEAR SCIENCE AND TECHNIQUES 24.4(2013). |
入库方式: OAI收割
来源:近代物理研究所
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